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Message-ID: <20221124083510.3008139-3-mmaddireddy@nvidia.com>
Date: Thu, 24 Nov 2022 14:05:09 +0530
From: Manikanta Maddireddy <mmaddireddy@...dia.com>
To: <vkoul@...nel.org>, <kishon@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <vidyas@...dia.com>
CC: <linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <bhelgaas@...gle.com>,
<lpieralisi@...nel.org>, <nkristam@...dia.com>,
Manikanta Maddireddy <mmaddireddy@...dia.com>
Subject: [PATCH 2/3] arm64: tegra: Add uphy lane number and intr in p2u nodes
UPHY lane number is required to exchange lane margin data between P2U
and UPHY. Add uphy lane number in p2u device tree nodes.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@...dia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 120 +++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index eaf05ee9acd1..ec8a28a9d380 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -1109,6 +1109,11 @@ p2u_hsio_0: phy@...0000 {
reg = <0x03e00000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 336 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 0>;
+
#phy-cells = <0>;
};
@@ -1117,6 +1122,11 @@ p2u_hsio_1: phy@...0000 {
reg = <0x03e10000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 337 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 1>;
+
#phy-cells = <0>;
};
@@ -1125,6 +1135,11 @@ p2u_hsio_2: phy@...0000 {
reg = <0x03e20000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 338 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 2>;
+
#phy-cells = <0>;
};
@@ -1133,6 +1148,11 @@ p2u_hsio_3: phy@...0000 {
reg = <0x03e30000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 339 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 3>;
+
#phy-cells = <0>;
};
@@ -1141,6 +1161,11 @@ p2u_hsio_4: phy@...0000 {
reg = <0x03e40000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 340 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 4>;
+
#phy-cells = <0>;
};
@@ -1149,6 +1174,11 @@ p2u_hsio_5: phy@...0000 {
reg = <0x03e50000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 341 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 5>;
+
#phy-cells = <0>;
};
@@ -1157,6 +1187,11 @@ p2u_hsio_6: phy@...0000 {
reg = <0x03e60000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 342 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 6>;
+
#phy-cells = <0>;
};
@@ -1165,6 +1200,11 @@ p2u_hsio_7: phy@...0000 {
reg = <0x03e70000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 343 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 7>;
+
#phy-cells = <0>;
};
@@ -1173,6 +1213,11 @@ p2u_nvhs_0: phy@...0000 {
reg = <0x03e90000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 344 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 8>;
+
#phy-cells = <0>;
};
@@ -1181,6 +1226,11 @@ p2u_nvhs_1: phy@...0000 {
reg = <0x03ea0000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 345 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 9>;
+
#phy-cells = <0>;
};
@@ -1189,6 +1239,11 @@ p2u_nvhs_2: phy@...0000 {
reg = <0x03eb0000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 346 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 10>;
+
#phy-cells = <0>;
};
@@ -1197,6 +1252,11 @@ p2u_nvhs_3: phy@...0000 {
reg = <0x03ec0000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 347 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 11>;
+
#phy-cells = <0>;
};
@@ -1205,6 +1265,11 @@ p2u_nvhs_4: phy@...0000 {
reg = <0x03ed0000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 348 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 12>;
+
#phy-cells = <0>;
};
@@ -1213,6 +1278,11 @@ p2u_nvhs_5: phy@...0000 {
reg = <0x03ee0000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 349 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 13>;
+
#phy-cells = <0>;
};
@@ -1221,6 +1291,11 @@ p2u_nvhs_6: phy@...0000 {
reg = <0x03ef0000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 350 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 14>;
+
#phy-cells = <0>;
};
@@ -1229,6 +1304,11 @@ p2u_nvhs_7: phy@...0000 {
reg = <0x03f00000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 351 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 15>;
+
#phy-cells = <0>;
};
@@ -1237,6 +1317,11 @@ p2u_gbe_0: phy@...0000 {
reg = <0x03f20000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 203 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 16>;
+
#phy-cells = <0>;
};
@@ -1245,6 +1330,11 @@ p2u_gbe_1: phy@...0000 {
reg = <0x03f30000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 220 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 17>;
+
#phy-cells = <0>;
};
@@ -1253,6 +1343,11 @@ p2u_gbe_2: phy@...0000 {
reg = <0x03f40000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 221 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 18>;
+
#phy-cells = <0>;
};
@@ -1261,6 +1356,11 @@ p2u_gbe_3: phy@...0000 {
reg = <0x03f50000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 222 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 19>;
+
#phy-cells = <0>;
};
@@ -1269,6 +1369,11 @@ p2u_gbe_4: phy@...0000 {
reg = <0x03f60000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 108 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 20>;
+
#phy-cells = <0>;
};
@@ -1277,6 +1382,11 @@ p2u_gbe_5: phy@...0000 {
reg = <0x03f70000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 109 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 21>;
+
#phy-cells = <0>;
};
@@ -1285,6 +1395,11 @@ p2u_gbe_6: phy@...0000 {
reg = <0x03f80000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 110 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 22>;
+
#phy-cells = <0>;
};
@@ -1293,6 +1408,11 @@ p2u_gbe_7: phy@...0000 {
reg = <0x03f90000 0x10000>;
reg-names = "ctl";
+ interrupts = <0 111 0x04>;
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 23>;
+
#phy-cells = <0>;
};
--
2.25.1
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