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Message-ID: <72b3d10e-5a8e-ed42-6808-f53773913422@starfivetech.com>
Date: Fri, 25 Nov 2022 14:41:12 +0800
From: Hal Feng <hal.feng@...rfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
CC: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-clk@...r.kernel.org>, Conor Dooley <conor@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Stephen Boyd <sboyd@...nel.org>,
"Michael Turquette" <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 09/14] dt-bindings: clock: Add StarFive JH7110 system
clock and reset generator
On Mon, 21 Nov 2022 09:47:08 +0100, Krzysztof Kozlowski wrote:
> On 18/11/2022 02:06, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@...il.dk>
> >
> > Add bindings for the system clock and reset generator (SYSCRG) on the
> > JH7110 RISC-V SoC by StarFive Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
> > Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
>
> Binding headers are coming with the file bringing bindings for the
> device, so you need to squash patches.
As we discussed in patch 7, could I merge patch 7, 8, 9, 10 and add the
following files in one commit?
include/dt-bindings/clock/starfive,jh7110-crg.h
include/dt-bindings/reset/starfive,jh7110-crg.h
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
Best regards,
Hal
>
> > ---
> > .../clock/starfive,jh7110-syscrg.yaml | 80 +++++++++++++++++++
> > MAINTAINERS | 2 +-
> > 2 files changed, 81 insertions(+), 1 deletion(-)
> > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
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