lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <Y4IxdOPWhLLg5rwd@spud> Date: Sat, 26 Nov 2022 15:32:04 +0000 From: Conor Dooley <conor@...nel.org> To: Samuel Holland <samuel@...lland.org> Cc: Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Anup Patel <apatel@...tanamicro.com>, Heinrich Schuchardt <heinrich.schuchardt@...onical.com>, Paul Walmsley <paul.walmsley@...ive.com>, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org Subject: Re: [PATCH] riscv: Fix NR_CPUS range conditions On Sat, Nov 26, 2022 at 12:15:56AM -0600, Samuel Holland wrote: > The conditions reference the symbol SBI_V01, which does not exist. The > correct symbol is RISCV_SBI_V01. Huh, good spot. Reviewed-by: Conor Dooley <conor.dooley@...rochip.com> > > Fixes: e623715f3d67 ("RISC-V: Increase range and default value of NR_CPUS") > Signed-off-by: Samuel Holland <samuel@...lland.org> > --- > > arch/riscv/Kconfig | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index fec54872ab45..acbfe34c6a00 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -319,9 +319,9 @@ config SMP > config NR_CPUS > int "Maximum number of CPUs (2-512)" > depends on SMP > - range 2 512 if !SBI_V01 > - range 2 32 if SBI_V01 && 32BIT > - range 2 64 if SBI_V01 && 64BIT > + range 2 512 if !RISCV_SBI_V01 > + range 2 32 if RISCV_SBI_V01 && 32BIT > + range 2 64 if RISCV_SBI_V01 && 64BIT > default "32" if 32BIT > default "64" if 64BIT > > -- > 2.37.4 >
Powered by blists - more mailing lists