linux-kernel - Re: [PATCH] riscv: Fix NR

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Date:   Mon, 28 Nov 2022 19:35:59 +0100
From:   Andrew Jones <ajones@...tanamicro.com>
To:     Conor Dooley <conor@...nel.org>
Cc:     Samuel Holland <samuel@...lland.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Anup Patel <apatel@...tanamicro.com>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH] riscv: Fix NR_CPUS range conditions

On Sat, Nov 26, 2022 at 03:32:04PM +0000, Conor Dooley wrote:
> On Sat, Nov 26, 2022 at 12:15:56AM -0600, Samuel Holland wrote:
> > The conditions reference the symbol SBI_V01, which does not exist. The
> > correct symbol is RISCV_SBI_V01.
> 
> Huh, good spot.
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Yeah, huh. It never occurred to me that we don't have some sort of symbol
referencing checking in kconfig. Or maybe we do and I just don't know how
to enable it? Anyway, this issue made me wonder how many more dangling
references we may have. I wrote a script to look for them and found 29,
including this one. I'm not exactly sure how to report them since they
touch so many different places. For now, I've opened this kernel BZ

https://bugzilla.kernel.org/show_bug.cgi?id=216748

> 
> > 
> > Fixes: e623715f3d67 ("RISC-V: Increase range and default value of NR_CPUS")
> > Signed-off-by: Samuel Holland <samuel@...lland.org>
> > ---
> > 
> >  arch/riscv/Kconfig | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index fec54872ab45..acbfe34c6a00 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -319,9 +319,9 @@ config SMP
> >  config NR_CPUS
> >  	int "Maximum number of CPUs (2-512)"
> >  	depends on SMP
> > -	range 2 512 if !SBI_V01
> > -	range 2 32 if SBI_V01 && 32BIT
> > -	range 2 64 if SBI_V01 && 64BIT
> > +	range 2 512 if !RISCV_SBI_V01
> > +	range 2 32 if RISCV_SBI_V01 && 32BIT
> > +	range 2 64 if RISCV_SBI_V01 && 64BIT

And for this patch,

Reviewed-by: Andrew Jones <ajones@...tanamicro.com>

Thanks,
drew