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Message-ID: <3819214.ElGaqSPkdT@diego>
Date: Mon, 28 Nov 2022 21:59:56 +0100
From: Heiko Stübner <heiko@...ech.de>
To: Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
linux-sunxi@...ts.linux.dev, Palmer Dabbelt <palmer@...belt.com>,
Conor Dooley <conor@...nel.org>,
linux-riscv@...ts.infradead.org,
Samuel Holland <samuel@...lland.org>
Cc: devicetree@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Jisheng Zhang <jszhang@...nel.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Andre Przywara <andre.przywara@....com>,
Samuel Holland <samuel@...lland.org>,
Albert Ou <aou@...s.berkeley.edu>,
Anup Patel <apatel@...tanamicro.com>,
Atish Patra <atishp@...osinc.com>,
Christian Hewitt <christianshewitt@...il.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Guo Ren <guoren@...nel.org>,
Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
Linus Walleij <linus.walleij@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Stanislav Jakubek <stano.jakubek@...il.com>
Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree
Am Samstag, 26. November 2022, 00:46:48 CET schrieb Samuel Holland:
> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
>
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
>
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
>
> The devicetrees are organized to minimize duplication:
> - Common perhiperals are described in sunxi-d1s-t113.dtsi
> - DSP-related peripherals are described in sunxi-d1-t113.dtsi
> - RISC-V specific hardware is described in sun20i-d1s.dtsi
> - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
>
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
>
> Signed-off-by: Samuel Holland <samuel@...lland.org>
While the overall dt looks good to me, it seems others did find
some minor issues. But I can at least provide a
Tested-by: Heiko Stuebner <heiko.stuebner@...ll.eu>
as it could sucessfully boot the Nezha variant of boards for me.
Heiko
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