linux-kernel - Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 28 Nov 2022 21:34:21 +0800
From:   Bin Meng <bmeng@...ylab.org>
To:     samuel@...lland.org
Cc:     andre.przywara@....com, aou@...s.berkeley.edu,
        apatel@...tanamicro.com, atishp@...osinc.com,
        christianshewitt@...il.com, conor.dooley@...rochip.com,
        conor@...nel.org, devicetree@...r.kernel.org, guoren@...nel.org,
        heiko@...ech.de, heinrich.schuchardt@...onical.com,
        jernej.skrabec@...il.com, jszhang@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, linus.walleij@...aro.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
        palmer@...belt.com, paul.walmsley@...ive.com, robh+dt@...nel.org,
        stano.jakubek@...il.com, wens@...e.org
Subject: Re: [PATCH v2 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
> 
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
> 
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
> 
> The devicetrees are organized to minimize duplication:
>  - Common perhiperals are described in sunxi-d1s-t113.dtsi
>  - DSP-related peripherals are described in sunxi-d1-t113.dtsi
>  - RISC-V specific hardware is described in sun20i-d1s.dtsi
>  - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
> 
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
> 
> Signed-off-by: Samuel Holland <samuel@...lland.org>
> ---
> 
> Changes in v2:
>  - Split into separate files for sharing with D1s/R528/T113
>  - Use SOC_PERIPHERAL_IRQ macro for interrupts
>  - Rename osc24M to dcxo and move the frequency to the board DTs
>  - Drop analog LDOs due to the missing binding
>  - Correct tcon_top DSI clock reference
>  - Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
>  - Add CPU OPP table
> 
>  arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi  |  66 ++
>  arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi |  76 ++
>  .../boot/dts/allwinner/sunxi-d1-t113.dtsi     |  15 +
>  .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 844 ++++++++++++++++++
>  4 files changed, 1001 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>  create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
>  create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
>  create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

<snip>
 
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <samuel@...lland.org>
> +
> +#define SOC_PERIPHERAL_IRQ(nr)	(nr + 16)
> +
> +#include "sunxi-d1s-t113.dtsi"
> +
> +/ {
> +	cpus {
> +		timebase-frequency = <24000000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "thead,c906", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			clocks = <&ccu CLK_RISCV>;
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <256>;
> +			d-cache-size = <32768>;
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <128>;
> +			i-cache-size = <32768>;
> +			mmu-type = "riscv,sv39";
> +			operating-points-v2 = <&opp_table_cpu>;
> +			riscv,isa = "rv64imafdc";
> +			#cooling-cells = <2>;
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +	};
> +
> +	opp_table_cpu: opp-table-cpu {
> +		compatible = "operating-points-v2";
> +
> +		opp-408000000 {
> +			opp-hz = /bits/ 64 <408000000>;
> +			opp-microvolt = <900000 900000 1100000>;
> +		};
> +
> +		opp-1080000000 {
> +			opp-hz = /bits/ 64 <1008000000>;
> +			opp-microvolt = <900000 900000 1100000>;
> +		};
> +	};
> +
> +	soc {
> +		interrupt-parent = <&plic>;
> +
> +		riscv_wdt: watchdog@...1000 {
> +			compatible = "allwinner,sun20i-d1-wdt";
> +			reg = <0x6011000 0x20>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&dcxo>, <&rtc CLK_OSC32K>;
> +			clock-names = "hosc", "losc";
> +		};
> +
> +		plic: interrupt-controller@...00000 {
> +			compatible = "allwinner,sun20i-d1-plic",
> +				     "thead,c900-plic";
> +			reg = <0x10000000 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 11>,
> +					      <&cpu0_intc 9>;
> +			interrupt-controller;
> +			riscv,ndev = <176>;

The D1-H user manual says starting from interrupt number 176, interrupts are
CPUX related which I assume are CPU internal interrupts?

If yes, for external ones, valid interrupt source range is [1, 175]. And this
field should be 175, no?

> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +		};
> +	};
> +};

<snip>

Regards,
Bin