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Message-ID: <a88349a2-94ac-1980-1998-a45ac5525f6b@ti.com>
Date: Tue, 29 Nov 2022 11:53:46 -0600
From: Andrew Davis <afd@...com>
To: Matt Ranostay <mranostay@...com>, <nm@...com>, <vigneshr@...com>,
<kristo@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <s-vadapalli@...com>,
<r-gunasekaran@...com>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v7 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device
tree node
On 11/22/22 4:16 AM, Matt Ranostay wrote:
> From: Aswath Govindraju <a-govindraju@...com>
>
> Add PCIe1 RC device tree node for the single PCIe instance present on
> the j721s2.
>
> Reviewed-by: Siddharth Vadapalli <s-vadapalli@...com>
> Signed-off-by: Aswath Govindraju <a-govindraju@...com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@...com>
> Signed-off-by: Matt Ranostay <mranostay@...com>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 41 ++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 2858ba589d54..27631ef32bf5 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -841,6 +841,47 @@ serdes0: serdes@...0000 {
> };
> };
>
> + pcie1_rc: pcie@...0000 {
NIT: Not sure we need to call this "_rc", and "1", 0 index these names for
consistency, "pcie0".
> + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
> + reg = <0x00 0x02910000 0x00 0x1000>,
> + <0x00 0x02917000 0x00 0x400>,
> + <0x00 0x0d800000 0x00 0x00800000>,
> + <0x00 0x18000000 0x00 0x00001000>;
> + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> + interrupt-names = "link_state";
> + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> + device_type = "pci";
> + ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
> + max-link-speed = <3>;
> + num-lanes = <4>;
> + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 276 41>;
> + clock-names = "fck";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x104c>;
> + device-id = <0xb013>;
> + msi-map = <0x0 &gic_its 0x0 0x10000>;
> + dma-coherent;
> + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
> + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> + #interrupt-cells = <1>;
Is this node the interrupt controller or is it the "interrupt-controller"?
Actually, what is that node? I don't see it in the binding docs..
Andrew
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
> + <0 0 0 2 &pcie1_intc 0>, /* INT B */
> + <0 0 0 3 &pcie1_intc 0>, /* INT C */
> + <0 0 0 4 &pcie1_intc 0>; /* INT D */
> +
> + pcie1_intc: interrupt-controller {
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
> + };
> + };
> +
> main_mcan0: can@...1000 {
> compatible = "bosch,m_can";
> reg = <0x00 0x02701000 0x00 0x200>,
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