linux-kernel - Re: [PATCH v7 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB

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Date:   Mon, 9 Jan 2023 09:37:14 +0530
From:   Vignesh Raghavendra <vigneshr@...com>
To:     Matt Ranostay <mranostay@...com>, <nm@...com>, <afd@...com>,
        <kristo@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <s-vadapalli@...com>,
        <r-gunasekaran@...com>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v7 1/8] arm64: dts: ti: k3-j721s2-main: Add support for
 USB



On 22/11/22 15:46, Matt Ranostay wrote:
> From: Aswath Govindraju <a-govindraju@...com>
> 
> Add support for single instance of USB 3.0 controller in J721S2 SoC.
> 
> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@...com>
> Signed-off-by: Aswath Govindraju <a-govindraju@...com>
> Signed-off-by: Matt Ranostay <mranostay@...com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 42 ++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 8915132efcc1..b4869bff4f22 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -26,6 +26,20 @@ l3cache-sram@...000 {
>  		};
>  	};
>  
> +	scm_conf: syscon@...000 {
> +		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
> +		reg = <0x00 0x00104000 0x00 0x18000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x00 0x00 0x00104000 0x18000>;
> +
> +		usb_serdes_mux: mux-controller-0 {

This needs binding update :(

+/workdir/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dtb: syscon@...000: 'mux-controller-0' does not match any of the regexes: '^clock-controller@[0-9a-f]+$', '^mux-controller@[0-9a-f]+$', 'phy@[0-9a-f]+$', 'pinctrl-[0-9]+'

make dtbs_check will warn here.


> +			compatible = "mmio-mux";
> +			#mux-control-cells = <1>;
> +			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
> +		};
> +	};
> +

[...]

-- 
Regards
Vignesh