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Message-ID: <202212010019.3EpbMgbM-lkp@intel.com>
Date: Thu, 1 Dec 2022 00:25:41 +0800
From: kernel test robot <lkp@...el.com>
To: Nicholas Piggin <npiggin@...il.com>
Cc: oe-kbuild-all@...ts.linux.dev, linux-kernel@...r.kernel.org,
Michael Ellerman <mpe@...erman.id.au>
Subject: arch/powerpc/include/asm/hw_irq.h:494 mtmsr_isync_irqsafe() warn:
inconsistent indenting
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 01f856ae6d0ca5ad0505b79bf2d22d7ca439b2a1
commit: 0fa6831811f62cfc10415d731bcf9fde2647ad81 powerpc/64: Fix msr_check_and_set/clear MSR[EE] race
date: 8 weeks ago
config: powerpc-randconfig-m041-20221128
compiler: powerpc-linux-gcc (GCC) 12.1.0
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
New smatch warnings:
arch/powerpc/include/asm/hw_irq.h:494 mtmsr_isync_irqsafe() warn: inconsistent indenting
Old smatch warnings:
arch/powerpc/include/asm/cpu_has_feature.h:12 early_cpu_has_feature() warn: bitwise AND condition is false here
arch/powerpc/kernel/process.c:445 giveup_all() warn: bitwise AND condition is false here
arch/powerpc/kernel/process.c:587 save_all() warn: bitwise AND condition is false here
arch/powerpc/include/asm/mmu.h:234 early_mmu_has_feature() warn: bitwise AND condition is false here
vim +494 arch/powerpc/include/asm/hw_irq.h
473
474 static inline unsigned long mtmsr_isync_irqsafe(unsigned long msr)
475 {
476 #ifdef CONFIG_PPC64
477 if (arch_irqs_disabled()) {
478 /*
479 * With soft-masking, MSR[EE] can change from 1 to 0
480 * asynchronously when irqs are disabled, and we don't want to
481 * set MSR[EE] back to 1 here if that has happened. A race-free
482 * way to do this is ensure EE is already 0. Another way it
483 * could be done is with a RESTART_TABLE handler, but that's
484 * probably overkill here.
485 */
486 msr &= ~MSR_EE;
487 mtmsr_isync(msr);
488 irq_soft_mask_set(IRQS_ALL_DISABLED);
489 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
490 } else
491 #endif
492 mtmsr_isync(msr);
493
> 494 return msr;
495 }
496
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