Date:   Thu, 1 Dec 2022 06:17:26 +0000
From:   JiaJie Ho <jiajie.ho@...rfivetech.com>
To:     "Conor.Dooley@...rochip.com" <Conor.Dooley@...rochip.com>
CC:     "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "herbert@...dor.apana.org.au" <herbert@...dor.apana.org.au>,
        "linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
        "kernel@...il.dk" <kernel@...il.dk>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>
Subject: RE: [PATCH 6/6] riscv: dts: starfive: Add crypto and DMA node for
 VisionFive 2



> -----Original Message-----
> From: Conor.Dooley@...rochip.com <Conor.Dooley@...rochip.com>
> Sent: Wednesday, November 30, 2022 5:31 PM
> To: JiaJie Ho <jiajie.ho@...rfivetech.com>
> Cc: robh+dt@...nel.org; herbert@...dor.apana.org.au; linux-
> crypto@...r.kernel.org; kernel@...il.dk; davem@...emloft.net;
> devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; linux-
> riscv@...ts.infradead.org; krzysztof.kozlowski+dt@...aro.org
> Subject: Re: [PATCH 6/6] riscv: dts: starfive: Add crypto and DMA node for
> VisionFive 2
> 
> Hey Jia Jie Ho,
> 
> On 30/11/2022 05:52, Jia Jie Ho wrote:
> > [You don't often get email from jiajie.ho@...rfivetech.com. Learn why
> > this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know
> > the content is safe
> >
> > Adding StarFive crypto IP and DMA controller node to VisionFive 2 SoC.
> >
> > Signed-off-by: Jia Jie Ho <jiajie.ho@...rfivetech.com>
> > Signed-off-by: Huan Feng <huan.feng@...rfivetech.com>
> 
> Out of curiosity, what was Huan Feng's contribution to this patch?
> Did they co-develop it, or is there some other reason?
> 
Hi Conor, 
Yes, Huan Feng co-developed this driver.

> > ---
> >   .../jh7110-starfive-visionfive-v2.dts         |  8 +++++
> >   arch/riscv/boot/dts/starfive/jh7110.dtsi      | 36 +++++++++++++++++++
> 
> I figure Emil will likely see anyway, but whenever you get actual review
> comments and send a v2 - please don't drop people that get_maintainer.pl
> tells you are responsible for the code in question.
> 
I will include everyone involved when sending the new patch series.

> >   2 files changed, 44 insertions(+)
> >
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> > index 450e920236a5..da2aa4d597f3 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> > @@ -115,3 +115,11 @@ &tdm_ext {
> >   &mclk_ext {
> >          clock-frequency = <49152000>;
> >   };
> > +
> > +&sec_dma {
> > +       status = "okay";
> > +};
> > +
> > +&crypto {
> > +       status = "okay";
> > +};
> 
> In what scenario would you not want to have these enabled?
> 
> Thanks,
> Conor.
> 
These drivers are always enabled. 
Is everything ok with the dts node entries?
Thank you for spending time reviewing and providing suggestions for this patch.

Regards,
Jia Jie

> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 4ac159d79d66..745a5650882c 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -455,5 +455,41 @@ uart5: serial@...20000 {
> >                          reg-shift = <2>;
> >                          status = "disabled";
> >                  };
> > +
> > +               sec_dma: sec_dma@...08000 {
> > +                       compatible = "arm,pl080", "arm,primecell";
> > +                       arm,primecell-periphid = <0x00041080>;
> > +                       reg = <0x0 0x16008000 0x0 0x4000>;
> > +                       reg-names = "sec_dma";
> > +                       interrupts = <29>;
> > +                       clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> > +                                <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> > +                       clock-names = "sec_hclk","apb_pclk";
> > +                       resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> > +                       reset-names = "sec_hre";
> > +                       lli-bus-interface-ahb1;
> > +                       mem-bus-interface-ahb1;
> > +                       memcpy-burst-size = <256>;
> > +                       memcpy-bus-width = <32>;
> > +                       #dma-cells = <2>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               crypto: crypto@...00000 {
> > +                       compatible = "starfive,jh7110-crypto";
> > +                       reg = <0x0 0x16000000 0x0 0x4000>;
> > +                       reg-names = "secreg";
> > +                       clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> > +                                <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> > +                       clock-names = "sec_hclk","sec_ahb";
> > +                       resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> > +                       reset-names = "sec_hre";
> > +                       enable-side-channel-mitigation;
> > +                       enable-dma;
> > +                       dmas = <&sec_dma 1 2>,
> > +                              <&sec_dma 0 2>;
> > +                       dma-names = "sec_m","sec_p";
> > +                       status = "disabled";
> > +               };
> >          };
> >   };
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@...ts.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

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