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Date: Tue, 6 Dec 2022 12:23:27 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: matthias.bgg@...il.com
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
nfraprado@...labora.com, kernel@...labora.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
Subject: [PATCH 2/5] arm64: dts: mt8192: Add complete CPU caches information
This SoC features two clusters composed of:
- 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
per-cpu 128KB L2 cache, 4-way set associative;
- 4x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative,
per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 2MB,
16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 424fc89cc6f7..3b5d49bf174d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -54,6 +54,12 @@ cpu0: cpu@0 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -65,6 +71,12 @@ cpu1: cpu@100 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -76,6 +88,12 @@ cpu2: cpu@200 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -87,6 +105,12 @@ cpu3: cpu@300 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -98,6 +122,12 @@ cpu4: cpu@400 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -109,6 +139,12 @@ cpu5: cpu@500 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -120,6 +156,12 @@ cpu6: cpu@600 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -131,6 +173,12 @@ cpu7: cpu@700 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -170,18 +218,28 @@ core3 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
};
idle-states {
--
2.38.1
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