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Date: Tue, 6 Dec 2022 12:23:26 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: matthias.bgg@...il.com
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
nfraprado@...labora.com, kernel@...labora.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
Subject: [PATCH 1/5] arm64: dts: mt8195: Add complete CPU caches information
This SoC features two clusters composed of:
- 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
per-cpu 128KB L2 cache, 4-way set associative;
- 4x Cortex A78: 64KB I-cache and 64KB D-cache, 4-way set associative,
per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 2MB,
16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 5d31536f4c48..539c49324d64 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -39,6 +39,12 @@ cpu0: cpu@0 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -52,6 +58,12 @@ cpu1: cpu@100 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -65,6 +77,12 @@ cpu2: cpu@200 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -78,6 +96,12 @@ cpu3: cpu@300 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -91,6 +115,12 @@ cpu4: cpu@400 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -104,6 +134,12 @@ cpu5: cpu@500 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -117,6 +153,12 @@ cpu6: cpu@600 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -130,6 +172,12 @@ cpu7: cpu@700 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -215,18 +263,28 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
};
};
--
2.38.1
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