linux-kernel - Re: [PATCH] arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes

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Message-ID: <7fcb4e87-7314-67c9-3217-48687f1ec86b@marcan.st>
Date:   Wed, 7 Dec 2022 13:29:11 +0900
From:   Hector Martin <marcan@...can.st>
To:     Janne Grunau <j@...nau.net>, Sven Peter <sven@...npeter.dev>,
        Alyssa Rosenzweig <alyssa@...enzweig.io>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc:     asahi@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: apple: Add t8103 L1/L2 cache properties and
 nodes

On 07/12/2022 07.38, Janne Grunau wrote:
> The t8103 CPU nodes are missing the cache hierarchy information. The
> cache hierarchy on Arm can not be detected and needs to be described in
> DT. The OS scheduler can make use of this information for scheduling
> decisions.
> 
> The cache size information is based on various articles about the
> processors. There's also an L3 system level cache (SLC). It's not
> described here because SLCs typically have some MMIO interface which
> would need to be described.
> 
> Based on Rob Herring's patch adding cache properties and nodes for
> t600x.
> 
> Link: https://lore.kernel.org/asahi/20221122220619.659174-1-robh@kernel.org/
> 
> Signed-off-by: Janne Grunau <j@...nau.net>

Acked-by: Hector Martin <marcan@...can.st>

Thanks! Applied to asahi-soc/dt.

- Hector