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Message-Id: <20221207101336.22264-1-jiasheng@iscas.ac.cn>
Date: Wed, 7 Dec 2022 18:13:36 +0800
From: Jiasheng Jiang <jiasheng@...as.ac.cn>
To: harry.wentland@....com, sunpeng.li@....com,
Rodrigo.Siqueira@....com, alexander.deucher@....com,
christian.koenig@....com, Xinhui.Pan@....com, airlied@...il.com,
daniel@...ll.ch, bas@...nieuwenhuizen.nl, Martin.Leung@....com,
Jun.Lei@....com, Chris.Park@....com, aurabindo.pillai@....com,
mwen@...lia.com
Cc: amd-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, Jiasheng Jiang <jiasheng@...as.ac.cn>
Subject: [PATCH] drm/amd/display: Add check for kzalloc
As kzalloc may fail and return NULL pointer, it should be better to check
the return value in order to avoid the NULL pointer dereference.
Moreover, dcn3_clk_mgr_construct should return the error and
should be checked cascadingly.
Fixes: 4d55b0dd1cdd ("drm/amd/display: Add DCN3 CLK_MGR")
Signed-off-by: Jiasheng Jiang <jiasheng@...as.ac.cn>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 9 ++++++---
.../gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 6 +++++-
.../gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h | 2 +-
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index f276abb63bcd..c08916bd5650 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -257,15 +257,18 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
return NULL;
}
if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
- dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+ if (dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg))
+ return NULL;
return &clk_mgr->base;
}
if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) {
- dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+ if (dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg))
+ return NULL;
return &clk_mgr->base;
}
if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) {
- dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+ if (dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg))
+ return NULL;
return &clk_mgr->base;
}
if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 3ce0ee0d012f..86c29dc45b70 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -517,7 +517,7 @@ struct clk_mgr_funcs dcn3_fpga_funcs = {
};
/*todo for dcn30 for clk register offset*/
-void dcn3_clk_mgr_construct(
+int dcn3_clk_mgr_construct(
struct dc_context *ctx,
struct clk_mgr_internal *clk_mgr,
struct pp_smu_funcs *pp_smu,
@@ -568,11 +568,15 @@ void dcn3_clk_mgr_construct(
dce_clock_read_ss_info(clk_mgr);
clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
+ if (!clk_mgr->base.bw_params)
+ return -ENOMEM;
/* need physical address of table to give to PMFW */
clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
&clk_mgr->wm_range_table_addr);
+
+ return 0;
}
void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
index 2cd95ec38266..8bdfed735184 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h
@@ -88,7 +88,7 @@
#endif
void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
-void dcn3_clk_mgr_construct(struct dc_context *ctx,
+int dcn3_clk_mgr_construct(struct dc_context *ctx,
struct clk_mgr_internal *clk_mgr,
struct pp_smu_funcs *pp_smu,
struct dccg *dccg);
--
2.25.1
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