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Date: Wed, 14 Dec 2022 07:57:46 +0000
From: "Zhang, Chen" <chen.zhang@...el.com>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
CC: "x86@...nel.org" <x86@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"Gao, Chao" <chao.gao@...el.com>,
Paolo Bonzini <pbonzini@...hat.com>,
"Christopherson,, Sean" <seanjc@...gle.com>,
"H. Peter Anvin" <hpa@...or.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Borislav Petkov <bp@...en8.de>, Ingo Molnar <mingo@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>
Subject: RE: [RFC PATCH 5/9] x86/bugs: Use Virtual MSRs to request hardware
mitigations
> -----Original Message-----
> From: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
> Sent: Tuesday, December 13, 2022 4:24 AM
> To: Zhang, Chen <chen.zhang@...el.com>
> Cc: x86@...nel.org; linux-kernel@...r.kernel.org; kvm@...r.kernel.org; Gao,
> Chao <chao.gao@...el.com>; Paolo Bonzini <pbonzini@...hat.com>;
> Christopherson,, Sean <seanjc@...gle.com>; H. Peter Anvin
> <hpa@...or.com>; Dave Hansen <dave.hansen@...ux.intel.com>; Borislav
> Petkov <bp@...en8.de>; Ingo Molnar <mingo@...hat.com>; Thomas Gleixner
> <tglx@...utronix.de>
> Subject: Re: [RFC PATCH 5/9] x86/bugs: Use Virtual MSRs to request hardware
> mitigations
>
> On Sun, Dec 11, 2022 at 12:00:42AM +0800, Zhang Chen wrote:
> > From: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
> >
> > Guests that have different family/model than the host may not be aware
> > of hardware mitigations(such as RRSBA_DIS_S) available on host. This
> > is particularly true when guests migrate. To solve this problem Intel
> > processors have added a virtual MSR interface through which guests can
> > report their mitigation status and request VMM to deploy relevant
> > hardware mitigations.
> >
> > Use this virtualized MSR interface to request relevant hardware
> > controls for retpoline mitigation.
> >
> > Signed-off-by: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
> > ---
> > arch/x86/include/asm/msr-index.h | 23 +++++++++++++++++++++++
> > arch/x86/kernel/cpu/bugs.c | 24 ++++++++++++++++++++++++
> > 2 files changed, 47 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/msr-index.h
> > b/arch/x86/include/asm/msr-index.h
> > index 1143ac9400c3..1166b472377c 100644
> > --- a/arch/x86/include/asm/msr-index.h
> > +++ b/arch/x86/include/asm/msr-index.h
> > @@ -165,6 +165,7 @@
> > *
> IA32_XAPIC_DISABLE_STATUS MSR
> > * supported
> > */
> > +#define ARCH_CAP_VIRTUAL_ENUM BIT(63) /*
> MSR_VIRTUAL_ENUMERATION supported */
> >
> > #define MSR_IA32_FLUSH_CMD 0x0000010b
> > #define L1D_FLUSH BIT(0) /*
> > @@ -1062,6 +1063,28 @@
> > #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
> > #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL <<
> 29)
> > #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
> > +
> > +/* Intel virtual MSRs */
> > +#define MSR_VIRTUAL_ENUMERATION 0x50000000
> > +#define VIRT_ENUM_MITIGATION_CTRL_SUPPORT BIT(0) /*
> > + * Mitigation ctrl via
> virtual
> > + * MSRs supported
> > + */
> > +
> > +#define MSR_VIRTUAL_MITIGATION_ENUM 0x50000001
> > +#define MITI_ENUM_BHB_CLEAR_SEQ_S_SUPPORT BIT(0) /* VMM
> supports BHI_DIS_S */
> > +#define MITI_ENUM_RETPOLINE_S_SUPPORT BIT(1) /*
> VMM supports RRSBA_DIS_S */
> > +
> > +#define MSR_VIRTUAL_MITIGATION_CTRL 0x50000002
> > +#define MITI_CTRL_BHB_CLEAR_SEQ_S_USED BIT(0) /*
> > + * Request VMM to
> deploy
> > + * BHI_DIS_S
> mitigation
> > + */
> > +#define MITI_CTRL_RETPOLINE_S_USED BIT(1) /*
> > + * Request VMM to
> deploy
> > + * RRSBA_DIS_S
> mitigation
> > + */
> > +
> > /* AMD-V MSRs */
> >
> > #define MSR_VM_CR 0xc0010114
> > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
> > index 3e3230cccaa7..a9e869f568ee 100644
> > --- a/arch/x86/kernel/cpu/bugs.c
> > +++ b/arch/x86/kernel/cpu/bugs.c
> > @@ -1379,6 +1379,28 @@ static void __init
> spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_
> > dump_stack();
> > }
> >
> > +/* Speculation control using virtualized MSRs */ static void __init
> > +spec_ctrl_setup_virtualized_msr(void)
> > +{
> > + u64 msr_virt_enum, msr_mitigation_enum, msr_mitigation_ctrl;
> > +
> > + if (!(x86_read_arch_cap_msr() & ARCH_CAP_VIRTUAL_ENUM))
> > + return;
> > +
> > + rdmsrl(MSR_VIRTUAL_ENUMERATION, msr_virt_enum);
> > + if (!(msr_virt_enum & VIRT_ENUM_MITIGATION_CTRL_SUPPORT))
> > + return;
> > +
> > + rdmsrl(MSR_VIRTUAL_MITIGATION_ENUM, msr_mitigation_enum);
> > + /* When retpoline is being used, request relevant hardware controls
> */
> > + if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&
> > + msr_mitigation_enum & MITI_ENUM_RETPOLINE_S_SUPPORT) {
> > + rdmsrl(MSR_VIRTUAL_MITIGATION_CTRL,
> msr_mitigation_ctrl);
> > + msr_mitigation_ctrl |= MITI_CTRL_RETPOLINE_S_USED;
> > + wrmsrl(MSR_VIRTUAL_MITIGATION_CTRL,
> msr_mitigation_ctrl);
> > + }
> > +}
> > +
> > static void __init spectre_v2_select_mitigation(void)
> > {
> > enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
> @@
> > -1485,6 +1507,8 @@ static void __init spectre_v2_select_mitigation(void)
> > mode == SPECTRE_V2_RETPOLINE)
> > spec_ctrl_disable_kernel_rrsba();
> >
> > + spec_ctrl_setup_virtualized_msr();
>
> I think this also needs to be called during secondary CPU initialization.
Yes, we need setup virtual MSRs for each CPU.
I will add the " spec_ctrl_setup_virtualized_msr()" to the "start_secondary()" in the arch/x86/kernel/smpboot.c next version.
Thanks
Chen
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