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Date: Thu, 15 Dec 2022 09:13:54 -0800
From: Reinette Chatre <reinette.chatre@...el.com>
To: Babu Moger <babu.moger@....com>, <corbet@....net>,
<tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>
CC: <fenghua.yu@...el.com>, <dave.hansen@...ux.intel.com>,
<x86@...nel.org>, <hpa@...or.com>, <paulmck@...nel.org>,
<akpm@...ux-foundation.org>, <quic_neeraju@...cinc.com>,
<rdunlap@...radead.org>, <damien.lemoal@...nsource.wdc.com>,
<songmuchun@...edance.com>, <peterz@...radead.org>,
<jpoimboe@...nel.org>, <pbonzini@...hat.com>,
<chang.seok.bae@...el.com>, <pawan.kumar.gupta@...ux.intel.com>,
<jmattson@...gle.com>, <daniel.sneddon@...ux.intel.com>,
<sandipan.das@....com>, <tony.luck@...el.com>,
<james.morse@....com>, <linux-doc@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <bagasdotme@...il.com>,
<eranian@...gle.com>, <christophe.leroy@...roup.eu>,
<jarkko@...nel.org>, <adrian.hunter@...el.com>,
<quic_jiles@...cinc.com>, <peternewman@...gle.com>
Subject: Re: [PATCH v9 05/13] x86/resctrl: Detect and configure Slow Memory
Bandwidth Allocation
Hi Babu,
On 12/1/2022 7:36 AM, Babu Moger wrote:
> The QoS slow memory configuration details are available via
> CPUID_Fn80000020_EDX_x02. Detect the available details and
> initialize the rest to defaults.
>
> Signed-off-by: Babu Moger <babu.moger@....com>
> ---
> arch/x86/include/asm/msr-index.h | 1 +
> arch/x86/kernel/cpu/resctrl/core.c | 36 +++++++++++++++++++++++++++--
> arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +-
> arch/x86/kernel/cpu/resctrl/rdtgroup.c | 8 ++++--
> 4 files changed, 41 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 37ff47552bcb..e0a40027aa62 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -1061,6 +1061,7 @@
>
> /* - AMD: */
> #define MSR_IA32_MBA_BW_BASE 0xc0000200
> +#define MSR_IA32_SMBA_BW_BASE 0xc0000280
>
> /* MSR_IA32_VMX_MISC bits */
> #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
> index 10a8c9d96f32..b4fc851f6489 100644
> --- a/arch/x86/kernel/cpu/resctrl/core.c
> +++ b/arch/x86/kernel/cpu/resctrl/core.c
> @@ -162,6 +162,13 @@ bool is_mba_sc(struct rdt_resource *r)
> if (!r)
> return rdt_resources_all[RDT_RESOURCE_MBA].r_resctrl.membw.mba_sc;
>
> + /*
> + * The software controller support is only applicable to MBA resource.
> + * Make sure to check for resource type.
> + */
> + if (r->rid != RDT_RESOURCE_MBA)
> + return false;
> +
> return r->membw.mba_sc;
> }
>
> @@ -225,9 +232,15 @@ static bool __rdt_get_mem_config_amd(struct rdt_resource *r)
> struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
> union cpuid_0x10_3_eax eax;
> union cpuid_0x10_x_edx edx;
> - u32 ebx, ecx;
> + u32 ebx, ecx, subleaf;
>
> - cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full);
> + /*
> + * Query CPUID_Fn80000020_EDX_x01 for MBA and
> + * CPUID_Fn80000020_EDX_x02 for SMBA
> + */
> + subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1;
> +
> + cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full);
> hw_res->num_closid = edx.split.cos_max + 1;
> r->default_ctrl = MAX_MBA_BW_AMD;
>
> @@ -750,6 +763,19 @@ static __init bool get_mem_config(void)
> return false;
> }
>
> +static __init bool get_slow_mem_config(void)
> +{
> + struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_SMBA];
> +
> + if (!rdt_cpu_has(X86_FEATURE_SMBA))
> + return false;
> +
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> + return __rdt_get_mem_config_amd(&hw_res->r_resctrl);
> +
> + return false;
> +}
> +
> static __init bool get_rdt_alloc_resources(void)
> {
> struct rdt_resource *r;
> @@ -780,6 +806,9 @@ static __init bool get_rdt_alloc_resources(void)
> if (get_mem_config())
> ret = true;
>
> + if (get_slow_mem_config())
> + ret = true;
> +
> return ret;
> }
>
> @@ -869,6 +898,9 @@ static __init void rdt_init_res_defs_amd(void)
> } else if (r->rid == RDT_RESOURCE_MBA) {
> hw_res->msr_base = MSR_IA32_MBA_BW_BASE;
> hw_res->msr_update = mba_wrmsr_amd;
> + } else if (r->rid == RDT_RESOURCE_SMBA) {
> + hw_res->msr_base = MSR_IA32_SMBA_BW_BASE;
> + hw_res->msr_update = mba_wrmsr_amd;
> }
> }
> }
> diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> index 1df0e3262bca..2dd4b8c47f23 100644
> --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> @@ -209,7 +209,7 @@ static int parse_line(char *line, struct resctrl_schema *s,
> unsigned long dom_id;
>
> if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP &&
> - r->rid == RDT_RESOURCE_MBA) {
> + (r->rid == RDT_RESOURCE_MBA || r->rid == RDT_RESOURCE_SMBA)) {
> rdt_last_cmd_puts("Cannot pseudo-lock MBA resource\n");
> return -EINVAL;
> }
> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
> index e5a48f05e787..8a3dafc0dbf7 100644
> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
> @@ -1213,7 +1213,7 @@ static bool rdtgroup_mode_test_exclusive(struct rdtgroup *rdtgrp)
>
> list_for_each_entry(s, &resctrl_schema_all, list) {
> r = s->res;
> - if (r->rid == RDT_RESOURCE_MBA)
> + if (r->rid == RDT_RESOURCE_MBA || r->rid == RDT_RESOURCE_SMBA)
> continue;
> has_cache = true;
> list_for_each_entry(d, &r->domains, list) {
> @@ -1402,7 +1402,8 @@ static int rdtgroup_size_show(struct kernfs_open_file *of,
> ctrl = resctrl_arch_get_config(r, d,
> closid,
> type);
> - if (r->rid == RDT_RESOURCE_MBA)
> + if (r->rid == RDT_RESOURCE_MBA ||
> + r->rid == RDT_RESOURCE_SMBA)
> size = ctrl;
> else
> size = rdtgroup_cbm_to_size(r, d, ctrl);
> @@ -2845,7 +2846,8 @@ static int rdtgroup_init_alloc(struct rdtgroup *rdtgrp)
>
> list_for_each_entry(s, &resctrl_schema_all, list) {
> r = s->res;
> - if (r->rid == RDT_RESOURCE_MBA) {
> + if (r->rid == RDT_RESOURCE_MBA ||
> + r->rid == RDT_RESOURCE_SMBA) {
> rdtgroup_init_mba(r, rdtgrp->closid);
> if (is_mba_sc(r))
> continue;
>
>
Reviewed-by: Reinette Chatre <reinette.chatre@...el.com>
Reinette
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