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Message-ID: <952b9e987996e694695a24581a86582186200a87.camel@mediatek.com>
Date: Tue, 20 Dec 2022 02:36:25 +0000
From: Allen-KH Cheng (程冠勳)
<Allen-KH.Cheng@...iatek.com>
To: "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"sboyd@...nel.org" <sboyd@...nel.org>,
"ikjn@...omium.org" <ikjn@...omium.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
Chun-Jie Chen (陳浚桀)
<Chun-Jie.Chen@...iatek.com>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
"wenst@...omium.org" <wenst@...omium.org>,
"angelogioacchino.delregno@...labora.com"
<angelogioacchino.delregno@...labora.com>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: RE: [PATCH 2/4] soc: mediatek: pm-domains: Add ADSP power domain data
for MT8192
Hi Matthias,
Thanks for the reminder. I will check this and resend next version.
Best Regards,
Allen
-----Original Message-----
From: Matthias Brugger <matthias.bgg@...il.com>
Sent: Friday, December 16, 2022 7:16 PM
To: Allen-KH Cheng (程冠勳) <Allen-KH.Cheng@...iatek.com>; Rob Herring <
robh+dt@...nel.org>; Krzysztof Kozlowski <
krzysztof.kozlowski+dt@...aro.org>; Chun-Jie Chen (陳浚桀) <
Chun-Jie.Chen@...iatek.com>; Stephen Boyd <sboyd@...nel.org>; Ikjoon
Jang <ikjn@...omium.org>
Cc: Project_Global_Chrome_Upstream_Group <
Project_Global_Chrome_Upstream_Group@...iatek.com>;
angelogioacchino.delregno@...labora.com; devicetree@...r.kernel.org;
linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
linux-mediatek@...ts.infradead.org; Chen-Yu Tsai <wenst@...omium.org>
Subject: Re: [PATCH 2/4] soc: mediatek: pm-domains: Add ADSP power
domain data for MT8192
On 15/12/2022 13:00, Allen-KH Cheng wrote:
> Add ADSP pm-domains (mtcmos) data for MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
> ---
> drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h
> b/drivers/soc/mediatek/mt8192-pm-domains.h
> index b97b2051920f..19e58f0ca1df 100644
> --- a/drivers/soc/mediatek/mt8192-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8192-pm-domains.h
> @@ -287,6 +287,22 @@ static const struct scpsys_domain_data
> scpsys_domain_data_mt8192[] = {
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> + [MT8192_POWER_DOMAIN_ADSP] = {
> + .name = "adsp",
> + .sta_mask = BIT(22),
> + .ctl_offs = 0x0358,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .ext_buck_iso_offs = 0x039C,
> + .ext_buck_iso_mask = BIT(2),
Not defined in upstream. It seems we are missing something here.
Regards,
Matthias
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP,
> + MT8192_TOP_AXI_PROT_EN_2_SET,
> + MT8192_TOP_AXI_PROT_EN_2_CLR,
> + MT8192_TOP_AXI_PROT_EN_2_STA1),
> + },
> + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO,
> + },
> [MT8192_POWER_DOMAIN_CAM] = {
> .name = "cam",
> .sta_mask = BIT(23),
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