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Date: Sat, 31 Dec 2022 13:58:54 +0100
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: linux-arm-msm@...r.kernel.org, andersson@...nel.org,
agross@...nel.org, krzysztof.kozlowski@...aro.org
Cc: marijn.suijten@...ainline.org,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH 01/18] arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digits
Some addresses were 7-hex-digits long, or less. Fix that.
Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 67 ++++++++++++++++++++++-----
1 file changed, 55 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 2ceae73a6069..17e15a06254f 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -146,7 +146,7 @@ reserved-memory {
ranges;
rpm_msg_ram: memory@...00 {
- reg = <0x0 0x60000 0x0 0x6000>;
+ reg = <0x0 0x00060000 0x0 0x6000>;
no-map;
};
@@ -181,7 +181,7 @@ soc: soc {
prng: qrng@...00 {
compatible = "qcom,prng-ee";
- reg = <0x0 0xe3000 0x0 0x1000>;
+ reg = <0x0 0x000e3000 0x0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
@@ -366,6 +366,49 @@ qpic_nand: nand-controller@...0000 {
status = "disabled";
};
+ usb3: usb@...8800 {
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+ reg = <0x0 0x08af8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <133330000>,
+ <20000000>;
+
+ resets = <&gcc GCC_USB0_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@...0000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x08a00000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ clocks = <&xo>;
+ clock-names = "ref";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
intc: interrupt-controller@...0000 {
compatible = "qcom,msm-qgic2";
#address-cells = <2>;
@@ -388,7 +431,7 @@ v2m@0 {
pcie_phy: phy@...00 {
compatible = "qcom,ipq6018-qmp-pcie-phy";
- reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@@ -404,10 +447,10 @@ pcie_phy: phy@...00 {
"common";
pcie_phy0: phy@...00 {
- reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
- <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
- <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
- <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
@@ -623,7 +666,7 @@ mdio: mdio@...00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
- reg = <0x0 0x90000 0x0 0x64>;
+ reg = <0x0 0x00090000 0x0 0x64>;
clocks = <&gcc GCC_MDIO_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
@@ -631,7 +674,7 @@ mdio: mdio@...00 {
qusb_phy_1: qusb@...00 {
compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x059000 0x0 0x180>;
+ reg = <0x0 0x00059000 0x0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
@@ -664,7 +707,7 @@ usb2: usb@...8800 {
dwc_1: usb@...0000 {
compatible = "snps,dwc3";
- reg = <0x0 0x7000000 0x0 0xcd00>;
+ reg = <0x0 0x07000000 0x0 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>;
phy-names = "usb2-phy";
@@ -679,7 +722,7 @@ dwc_1: usb@...0000 {
ssphy_0: ssphy@...00 {
compatible = "qcom,ipq6018-qmp-usb3-phy";
- reg = <0x0 0x78000 0x0 0x1c4>;
+ reg = <0x0 0x00078000 0x0 0x1c4>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -708,7 +751,7 @@ usb0_ssphy: phy@...00 {
qusb_phy_0: qusb@...00 {
compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x079000 0x0 0x180>;
+ reg = <0x0 0x00079000 0x0 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
--
2.39.0
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