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Message-ID: <Y7iu0RC9jgWh7hfJ@spud>
Date: Fri, 6 Jan 2023 23:29:21 +0000
From: Conor Dooley <conor@...nel.org>
To: Arnd Bergmann <arnd@...db.de>
Cc: Prabhakar <prabhakar.csengg@...il.com>,
"Conor.Dooley" <conor.dooley@...rochip.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Heiko Stübner <heiko@...ech.de>,
guoren <guoren@...nel.org>,
Andrew Jones <ajones@...tanamicro.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
"open list:RISC-V ARCHITECTURE" <linux-riscv@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>,
devicetree@...r.kernel.org,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@...renesas.com>,
Philipp Tomsich <philipp.tomsich@...ll.eu>,
Nathan Chancellor <nathan@...nel.org>,
Atish Patra <atishp@...osinc.com>,
Anup Patel <apatel@...tanamicro.com>,
Tsukasa OI <research_trasio@....a4lg.com>,
Jisheng Zhang <jszhang@...nel.org>,
Mayuresh Chitale <mchitale@...tanamicro.com>
Subject: Re: [RFC PATCH v6 1/6] riscv: mm: dma-noncoherent: Switch using
function pointers for cache management
On Fri, Jan 06, 2023 at 11:31:33PM +0100, Arnd Bergmann wrote:
> On Fri, Jan 6, 2023, at 19:55, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > +struct riscv_cache_ops zicbom_cmo_ops = {
> > + .clean_range = &zicbom_cmo_clean_range,
> > + .inv_range = &zicbom_cmo_inval_range,
> > + .flush_range = &zicbom_cmo_flush_range,
> > +};
> > +#else
> > +struct riscv_cache_ops zicbom_cmo_ops = {
> > + .clean_range = NULL,
> > + .inv_range = NULL,
> > + .flush_range = NULL,
> > + .riscv_dma_noncoherent_cmo_ops = NULL,
> > +};
> > +#endif
> > +EXPORT_SYMBOL(zicbom_cmo_ops);
>
> Same here: If the ZICBOM ISA is disabled, nothing should
> reference zicbom_cmo_ops.
> Also, since ZICBOM is a standard
> extension, I think it makes sense to always have it enabled,
> at least whenever noncoherent DMA is supported, that way
> it can be the default that gets used in the absence of any
> nonstandard cache controller.
While I think of it, this is not possible as Zicbom requires toolchain
support whereas the alternative methods for non-coherent DMA do not.
Thanks,
Conor.
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