linux-kernel - Re: [PATCH 1/4] dts: add riscv include prefix link

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Message-ID: <Y7r6TLTm1r+IlrYj@spud>
Date:   Sun, 8 Jan 2023 17:15:56 +0000
From:   Conor Dooley <conor@...nel.org>
To:     Andre Przywara <andre.przywara@....com>
Cc:     Samuel Holland <samuel@...lland.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        Chen-Yu Tsai <wens@...e.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Icenowy Zheng <uwu@...nowy.me>,
        András Szemzö <szemzo.andras@...il.com>,
        Fabien Poussin <fabien.poussin@...il.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-sunxi@...ts.linux.dev, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, Frank Rowand <frowand.list@...il.com>
Subject: Re: [PATCH 1/4] dts: add riscv include prefix link

On Fri, Jan 06, 2023 at 01:01:52AM +0000, Andre Przywara wrote:
> The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
> die as their R528/T113-s siblings with ARM Cortex-A7 cores.
> 
> To allow sharing the basic SoC .dtsi files across those two
> architectures as well, introduce a symlink to the RISC-V DT directory.

Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Thanks,
Conor.

> 
> Signed-off-by: Andre Przywara <andre.przywara@....com>
> ---
>  scripts/dtc/include-prefixes/riscv | 1 +
>  1 file changed, 1 insertion(+)
>  create mode 120000 scripts/dtc/include-prefixes/riscv
> 
> diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
> new file mode 120000
> index 0000000000000..2025094189380
> --- /dev/null
> +++ b/scripts/dtc/include-prefixes/riscv
> @@ -0,0 +1 @@
> +../../../arch/riscv/boot/dts
> \ No newline at end of file
> -- 
> 2.35.5
> 
> 

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