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Message-ID: <CAL_JsqLFSMzmTSAjtWWotzFy=JLr+rjim4F_X5thWK9ji6z22g@mail.gmail.com>
Date:   Mon, 9 Jan 2023 14:18:41 -0600
From:   Rob Herring <robh@...nel.org>
To:     Mark Brown <broonie@...nel.org>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Will Deacon <will@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Marc Zyngier <maz@...nel.org>,
        James Morse <james.morse@....com>,
        Alexandru Elisei <alexandru.elisei@....com>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Oliver Upton <oliver.upton@...ux.dev>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kvmarm@...ts.linux.dev, linux-perf-users@...r.kernel.org,
        James Clark <james.clark@....com>
Subject: Re: [PATCH v4 3/8] arm64/sysreg: Convert SPE registers to automatic generation

On Mon, Jan 9, 2023 at 1:33 PM Mark Brown <broonie@...nel.org> wrote:
>
> On Mon, Jan 09, 2023 at 01:26:19PM -0600, Rob Herring wrote:
> > Convert all the SPE register defines to automatic generation. No
> > functional changes.
> >
> > New registers and fields for SPEv1.2 are added with the conversion.
> >
> > Some of the PMBSR MSS field defines are kept as the automatic generation
> > has no way to create multiple names for the same register bits. The
> > meaning of the MSS field depends on other bits.
> >
> > Tested-by: James Clark <james.clark@....com>
> > Signed-off-by: Rob Herring <robh@...nel.org>
> > ---
> > v4:
> >  - Rebase on v6.2-rc1
> > v3:
> >  - Make some fields enums and add some missing fields
>
> What changed to invalidate my Reviewed-by?
>
>    https://lore.kernel.org/all/Y2kgC9QlBwvXTLe6@sirena.org.uk/

Ugg, sorry. Nothing changed, I just forgot to add it.

Rob

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