linux-kernel - Re: [RESEND RFC PATCH v5 3/5] ARM: dts: stm32: add CAN support on stm32f429

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Message-ID: <b2a88e83-2eac-7b58-4803-b020c0336e34@foss.st.com>
Date:   Mon, 9 Jan 2023 15:45:10 +0100
From:   Alexandre TORGUE <alexandre.torgue@...s.st.com>
To:     Dario Binacchi <dario.binacchi@...rulasolutions.com>,
        <linux-kernel@...r.kernel.org>
CC:     Vincent Mailhol <mailhol.vincent@...adoo.fr>,
        Amarula patchwork <linux-amarula@...rulasolutions.com>,
        Marc Kleine-Budde <mkl@...gutronix.de>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Rob Herring <robh@...nel.org>, <michael@...rulasolutions.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Rob Herring <robh+dt@...nel.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-stm32@...md-mailman.stormreply.com>
Subject: Re: [RESEND RFC PATCH v5 3/5] ARM: dts: stm32: add CAN support on
 stm32f429

On 1/8/23 17:25, Dario Binacchi wrote:
> Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The
> chip contains two CAN peripherals, CAN1 the master and CAN2 the slave,
> that share some of the required logic like clock and filters. This means
> that the slave CAN can't be used without the master CAN.
> 
> Signed-off-by: Dario Binacchi <dario.binacchi@...rulasolutions.com>
> 
> ---
> 
> (no changes since v4)
> 
> Changes in v4:
> - Replace the node can@...06400 (compatible "st,stm32f4-bxcan-core")
>    with the gcan@...06600 node ("sysnode" compatible). The gcan node
>    contains clocks and memory addresses shared by the two can nodes
>    of which it's no longer the parent.
> - Add to can nodes the "st,gcan" property (global can memory) which
>    references the gcan@...06600 node ("sysnode compatibble).
> 
> Changes in v3:
> - Remove 'Dario Binacchi <dariobin@...ero.it>' SOB.
> - Add "clocks" to can@0 node.
> 
>   arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++
>   1 file changed, 29 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index c31ceb821231..ce08872109b8 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -362,6 +362,35 @@ i2c3: i2c@...05c00 {
>   			status = "disabled";
>   		};
>   
> +		gcan: gcan@...06600 {
> +			compatible = "st,stm32f4-gcan", "syscon";
> +			reg = <0x40006600 0x200>;
> +			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
> +		};
> +
> +		can1: can@...06400 {
> +			compatible = "st,stm32f4-bxcan";
> +			reg = <0x40006400 0x200>;
> +			interrupts = <19>, <20>, <21>, <22>;
> +			interrupt-names = "tx", "rx0", "rx1", "sce";
> +			resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
> +			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
> +			st,can-master;
> +			st,gcan = <&gcan>;
> +			status = "disabled";
> +		};

We try to keep ordering by address. Can you move can1 before gcan ?
Otherwise, it is ok for me.

> +
> +		can2: can@...06800 {
> +			compatible = "st,stm32f4-bxcan";
> +			reg = <0x40006800 0x200>;
> +			interrupts = <63>, <64>, <65>, <66>;
> +			interrupt-names = "tx", "rx0", "rx1", "sce";
> +			resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
> +			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
> +			st,gcan = <&gcan>;
> +			status = "disabled";
> +		};
> +
>   		dac: dac@...07400 {
>   			compatible = "st,stm32f4-dac-core";
>   			reg = <0x40007400 0x400>;