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Message-ID: <895daf8d-3303-ac70-16ab-76bead23d389@arm.com>
Date: Tue, 10 Jan 2023 14:24:22 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: Rob Herring <robh@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
Will Deacon <will@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Catalin Marinas <catalin.marinas@....com>,
Marc Zyngier <maz@...nel.org>,
James Morse <james.morse@....com>,
Alexandru Elisei <alexandru.elisei@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Oliver Upton <oliver.upton@...ux.dev>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
Namhyung Kim <namhyung@...nel.org>
Cc: Mark Brown <broonie@...nel.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kvmarm@...ts.linux.dev, linux-perf-users@...r.kernel.org,
James Clark <james.clark@....com>
Subject: Re: [PATCH v4 6/8] perf: arm_spe: Support new SPEv1.2/v8.7 'not
taken' event
On 1/10/23 00:56, Rob Herring wrote:
> Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of
> the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the
> additional event.
>
> Tested-by: James Clark <james.clark@....com>
> Signed-off-by: Rob Herring <robh@...nel.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@....com>
> ---
> v4:
> - Rebase on v6.2-rc1
> v3:
> - No change
> v2:
> - Update for v6.1 sysreg generated header changes
> ---
> arch/arm64/include/asm/sysreg.h | 2 ++
> drivers/perf/arm_spe_pmu.c | 4 +++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index db269eda7c1c..fc8787727792 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -221,6 +221,8 @@
> BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
> #define PMSEVFR_EL1_RES0_V1P1 \
> (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
> +#define PMSEVFR_EL1_RES0_V1P2 \
> + (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
>
> /* Buffer error reporting */
> #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
> index af6d3867c3e7..82f67e941bc4 100644
> --- a/drivers/perf/arm_spe_pmu.c
> +++ b/drivers/perf/arm_spe_pmu.c
> @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver)
> case ID_AA64DFR0_EL1_PMSVer_IMP:
> return PMSEVFR_EL1_RES0_IMP;
> case ID_AA64DFR0_EL1_PMSVer_V1P1:
> + return PMSEVFR_EL1_RES0_V1P1;
> + case ID_AA64DFR0_EL1_PMSVer_V1P2:
> /* Return the highest version we support in default */
> default:
> - return PMSEVFR_EL1_RES0_V1P1;
> + return PMSEVFR_EL1_RES0_V1P2;
> }
> }
>
>
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