linux-kernel - RE: NXP imx6ull nonalignment buffer question

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Message-ID: <DB7PR04MB4010D6ABA0D10AB826F468CC90C29@DB7PR04MB4010.eurprd04.prod.outlook.com>
Date:   Fri, 13 Jan 2023 03:30:21 +0000
From:   Bough Chen <haibo.chen@....com>
To:     Michael Nazzareno Trimarchi <michael@...rulasolutions.com>,
        Shawn Guo <shawnguo@...nel.org>,
        Fabio Estevam <festevam@...il.com>,
        LKML <linux-kernel@...r.kernel.org>
CC:     linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        Ulf Hansson <ulf.hansson@...aro.org>
Subject: RE: NXP imx6ull nonalignment buffer question

> -----Original Message-----
> From: Michael Nazzareno Trimarchi <michael@...rulasolutions.com>
> Sent: 2023年1月9日 21:02
> To: Bough Chen <haibo.chen@....com>; Shawn Guo <shawnguo@...nel.org>;
> Fabio Estevam <festevam@...il.com>; LKML <linux-kernel@...r.kernel.org>
> Cc: linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>;
> linux-mmc@...r.kernel.org; Ulf Hansson <ulf.hansson@...aro.org>
> Subject: NXP imx6ull nonalignment buffer question
> 
> Hi Haibo
> 
> Working on imx6ulz design and found that if I send a sdio packet using the
> sdio_writesb the adma driver tries to handle it with two dma descriptors. The
> first one filled with the bytes up to 3 to cover the misalign and then another
> buffer descriptor
> 
>   offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
>                          SDHCI_ADMA2_MASK;
>                 if (offset) {
>                         if (data->flags & MMC_DATA_WRITE) {
>                                 buffer = sdhci_kmap_atomic(sg);
>                                 memcpy(align, buffer, offset);
>                                 sdhci_kunmap_atomic(buffer);
>                         }
> 
>                         /* tran, valid */
>                         __sdhci_adma_write_desc(host, &desc,
> align_addr,
>                                                 offset,
> ADMA2_TRAN_VALID);
> 
>                         BUG_ON(offset > 65536);
> 
>                         align += SDHCI_ADMA2_ALIGN;
>                         align_addr += SDHCI_ADMA2_ALIGN;
> 
>                         addr += offset;
>                         len -= offset;
>                 }
> 
> In 48.7.4 Data Length Setting
> For either ADMA (ADMA1 or ADMA2) transfer, the data in the data buffer must
> be word aligned, so the data length set in the descriptor must be a multiple of 4.
> I have noticed that this code does not work as expected.

Hi Michael,

My understanding is: for the sentence " the data in the data buffer must be word aligned", this means the start address of the data must be word aligned, but not limit the data length.

Best Regards
Haibo Chen
> 
> Did you have any feedback?
> 
> Michael