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Message-ID: <87v8l61l3m.fsf@miraculix.mork.no>
Date: Mon, 16 Jan 2023 17:48:45 +0100
From: Bjørn Mork <bjorn@...k.no>
To: "Russell King (Oracle)" <linux@...linux.org.uk>
Cc: Frank Wunderlich <frank-w@...lic-files.de>,
Frank Wunderlich <linux@...web.de>,
linux-mediatek@...ts.infradead.org,
Alexander Couzens <lynxis@...0.eu>,
Felix Fietkau <nbd@....name>, John Crispin <john@...ozen.org>,
Sean Wang <sean.wang@...iatek.com>,
Mark Lee <Mark-MC.Lee@...iatek.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Matthias Brugger <matthias.bgg@...il.com>,
netdev@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] net: mtk_sgmii: implement mtk_pcs_ops
"Russell King (Oracle)" <linux@...linux.org.uk> writes:
> I found the document for the PHY at:
>
> https://assets.maxlinear.com/web/documents/617792_gpy212b1vc_gpy212c0vc_ds_rev1.3.pdf
>
> It seems as I suspected, the PHY has not completed SGMII AN. Please
> can you read register 8 when operating at 1G speeds as well
> (VSPEC1_SGMII_CTRL)? Thanks.
Both phys at 1G:
root@...nWrt:/# mdio mdio-bus 5:30 raw 8
0x34da
root@...nWrt:/# mdio mdio-bus 6:30 raw 8
0x34da
Bjørn
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