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Message-ID: <83385cac-9b66-8236-6039-65332ea9edb3@linaro.org>
Date: Thu, 19 Jan 2023 11:41:52 +0100
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Bjorn Andersson <andersson@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, agross@...nel.org,
krzysztof.kozlowski@...aro.org, marijn.suijten@...ainline.org,
Amit Kucheria <amitk@...nel.org>,
Thara Gopinath <thara.gopinath@...il.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Zhang Rui <rui.zhang@...el.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
Loic Poulain <loic.poulain@...aro.org>,
Stephan Gerhold <stephan@...hold.net>,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org
Subject: Re: [PATCH 2/2] firmware: qcom_scm: Fully implement
qcom_scm_lmh_dcvsh()
On 19.01.2023 04:04, Bjorn Andersson wrote:
> On Fri, Jan 13, 2023 at 04:14:01AM +0100, Konrad Dybcio wrote:
>> The qcom_scm_lmh_dcvsh call can actually pass two values to the
>> secure world. The second value is used for example with the
>> LMH_FREQ_CAP function, which limits the maximum achievable frequency
>> directly from LMh. Add the missing arguments, handle them and update
>> the current usages of this function.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
>> ---
>> drivers/firmware/qcom_scm.c | 13 ++++++++-----
>> drivers/thermal/qcom/lmh.c | 28 ++++++++++++++--------------
>> include/linux/qcom_scm.h | 5 +++--
>> 3 files changed, 25 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
>> index cdbfe54c8146..58a19a47e442 100644
>> --- a/drivers/firmware/qcom_scm.c
>> +++ b/drivers/firmware/qcom_scm.c
>> @@ -1252,12 +1252,13 @@ int qcom_scm_lmh_profile_change(u32 profile_id)
>> }
>> EXPORT_SYMBOL(qcom_scm_lmh_profile_change);
>>
>> -int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
>> - u64 limit_node, u32 node_id, u64 version)
>> +int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val0,
>> + u32 payload_val1, u64 limit_node, u32 node_id,
>> + u64 version, bool has_val1)
>
> Rather than always passing a dummy payload_val1 and then having has_val1
> to indicate if it should be considered or not... how about moving the
> payload last in the call, as a va_list with a "count" before that?
Sounds neat, but..
>
> I.e:
>
> int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u64 limit_node, u32 node_id,
> u64 version, unsigned int payload_count, ...)
>
>> {
>> dma_addr_t payload_phys;
>> u32 *payload_buf;
>> - int ret, payload_size = 5 * sizeof(u32);
>> + int ret, payload_size = (5 + has_val1) * sizeof(u32);
>
> allocate 4 + payload_count
>
>>
>> struct qcom_scm_desc desc = {
>> .svc = QCOM_SCM_SVC_LMH,
>> @@ -1278,8 +1279,10 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
>> payload_buf[0] = payload_fn;
>> payload_buf[1] = 0;
>> payload_buf[2] = payload_reg;
>> - payload_buf[3] = 1;
>> - payload_buf[4] = payload_val;
>> + payload_buf[3] = has_val1 ? 2 : 1;
>> + payload_buf[4] = payload_val0;
>> + if (has_val1)
>> + payload_buf[5] = payload_val1;
>
> Something like:
>
> payload_buf[3] = payload_count;
> va_start(ap, payload_count);
> for (i = 0; i < payload_count; i++)
> payload_buf[4 + i] = va_arg(ap, uint32_t);
> va_end(ap);
..can the call accept more arguments? And will they be
interpreted in any way? Otherwise I may add also add
WARN_ON() or something like this to prevent user error.
>
>
>
> That said, I don't see a single "true" below. Perhaps I'm missing it? I
> would expect some code in the same series use the newly introduced
> logic.
Yeah there's no "true"s, this patch only refactored the
code in preparation for 8998/660, but adding them as-is
makes little sense before LMh_lite is also supported
(AFAIUU this LMh_normal part is just an interface for OSM
and the actual limits programming is either done on an
internal-consensus-between-all-3-blocks basis OR just by
LMh_lite. I can delay resending this series until the
changes are actually required if you prefer.
On newer SoCs LMh wakes up as part of OSM_secure/EPSS
programming and needs little to no configuration
externally (as you can see in this driver) and there's
no external _lite block.
Konrad
>
> Thanks,
> Bjorn
>
>>
>> desc.args[0] = payload_phys;
>>
>> diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
>> index 5e8ff196c9a6..d2b5ea8322eb 100644
>> --- a/drivers/thermal/qcom/lmh.c
>> +++ b/drivers/thermal/qcom/lmh.c
>> @@ -147,23 +147,23 @@ static int lmh_probe(struct platform_device *pdev)
>> return -EINVAL;
>>
>> if (flags & LMH_ENABLE_ALGOS) {
>> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
>> - LMH_NODE_DCVS, node_id, 0);
>> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1, 0,
>> + LMH_NODE_DCVS, node_id, 0, false);
>> if (ret)
>> dev_err(dev, "Error %d enabling current subfunction\n", ret);
>>
>> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
>> - LMH_NODE_DCVS, node_id, 0);
>> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1, 0,
>> + LMH_NODE_DCVS, node_id, 0, false);
>> if (ret)
>> dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
>>
>> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
>> - LMH_NODE_DCVS, node_id, 0);
>> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1, 0,
>> + LMH_NODE_DCVS, node_id, 0, false);
>> if (ret)
>> dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
>>
>> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
>> - LMH_NODE_DCVS, node_id, 0);
>> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1, 0,
>> + LMH_NODE_DCVS, node_id, 0, false);
>> if (ret) {
>> dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
>> return ret;
>> @@ -177,22 +177,22 @@ static int lmh_probe(struct platform_device *pdev)
>> }
>>
>> /* Set default thermal trips */
>> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm,
>> - LMH_NODE_DCVS, node_id, 0);
>> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_ARM_THRESHOLD, temp_arm, 0,
>> + LMH_NODE_DCVS, node_id, 0, false);
>> if (ret) {
>> dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
>> return ret;
>> }
>>
>> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high,
>> - LMH_NODE_DCVS, node_id, 0);
>> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_HI_THRESHOLD, temp_high, 0,
>> + LMH_NODE_DCVS, node_id, 0, false);
>> if (ret) {
>> dev_err(dev, "Error setting thermal HI threshold%d\n", ret);
>> return ret;
>> }
>>
>> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low,
>> - LMH_NODE_DCVS, node_id, 0);
>> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_TH_LOW_THRESHOLD, temp_low, 0,
>> + LMH_NODE_DCVS, node_id, 0, false);
>> if (ret) {
>> dev_err(dev, "Error setting thermal ARM threshold%d\n", ret);
>> return ret;
>> diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
>> index 1e449a5d7f5c..9fd798d17fdd 100644
>> --- a/include/linux/qcom_scm.h
>> +++ b/include/linux/qcom_scm.h
>> @@ -117,8 +117,9 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
>> extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
>> extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
>>
>> -extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
>> - u64 limit_node, u32 node_id, u64 version);
>> +extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val0,
>> + u32 payload_val1, u64 limit_node, u32 node_id,
>> + u64 version, bool has_val1);
>> extern int qcom_scm_lmh_profile_change(u32 profile_id);
>> extern bool qcom_scm_lmh_dcvsh_available(void);
>>
>> --
>> 2.39.0
>>
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