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Message-ID: <20230123095733.31657-9-r-gunasekaran@ti.com>
Date: Mon, 23 Jan 2023 15:27:33 +0530
From: Ravi Gunasekaran <r-gunasekaran@...com>
To: <nm@...com>, <afd@...com>, <vigneshr@...com>, <kristo@...nel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<s-vadapalli@...com>, <r-gunasekaran@...com>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v8 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
From: Aswath Govindraju <a-govindraju@...com>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@...com>
Signed-off-by: Aswath Govindraju <a-govindraju@...com>
Signed-off-by: Vignesh Raghavendra <vigneshr@...com>
Signed-off-by: Matt Ranostay <mranostay@...com>
Link: https://lore.kernel.org/r/20221122101616.770050-9-mranostay@ti.com
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@...com>
---
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 0503e690cfaf..561d70cdee9b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -374,6 +374,13 @@
};
};
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.17.1
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