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Message-ID: <Y9fOHxn8rdIHuDbn@lunn.ch>
Date: Mon, 30 Jan 2023 15:03:11 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Frank Sae <Frank.Sae@...or-comm.com>
Cc: Peter Geis <pgwipeout@...il.com>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
yanhong.wang@...rfivetech.com, xiaogang.fan@...or-comm.com,
fei.zhang@...or-comm.com, hua.sun@...or-comm.com,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH net-next v3 1/5] dt-bindings: net: Add Motorcomm yt8xxx
ethernet phy
On Mon, Jan 30, 2023 at 02:35:35PM +0800, Frank Sae wrote:
> Add a YAML binding document for the Motorcom yt8xxx Ethernet phy driver.
>
> Signed-off-by: Frank Sae <Frank.Sae@...or-comm.com>
> ---
> .../bindings/net/motorcomm,yt8xxx.yaml | 102 ++++++++++++++++++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> MAINTAINERS | 1 +
> 3 files changed, 105 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
> new file mode 100644
> index 000000000000..8527576c15b3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MotorComm yt8xxx Ethernet PHY
> +
> +maintainers:
> + - frank sae <frank.sae@...or-comm.com>
> +
> +allOf:
> + - $ref: ethernet-phy.yaml#
> +
> +properties:
> + rx-internal-delay-ps:
> + description: |
> + RGMII RX Clock Delay used only when PHY operates in RGMII mode with
> + internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
> + enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
> + 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
> + 2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
> + default: 1950
Ah! There has been a misunderstand. Yes, this changes does make sense, but ....
> +
> + tx-internal-delay-ps:
> + description: |
> + RGMII TX Clock Delay used only when PHY operates in RGMII mode with
> + internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
> + enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
> + 1950, 2100, 2250 ]
> + default: 150
... i was actually trying to say this 150 is odd. Why is this not
1950?
Andrew
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