linux-kernel - Re: [PATCH 09/10] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support

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Message-ID: <85ae379d-ee71-7636-1ca1-2fb2baad63f3@linaro.org>
Date:   Tue, 31 Jan 2023 20:24:49 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>,
        Konrad Dybcio <konrad.dybcio@...aro.org>, agross@...nel.org,
        andersson@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
        sboyd@...nel.org, ulf.hansson@...aro.org, linus.walleij@...aro.org,
        catalin.marinas@....com, will@...nel.org, shawnguo@...nel.org,
        arnd@...db.de, marcel.ziswiler@...adex.com,
        dmitry.baryshkov@...aro.org, nfraprado@...labora.com,
        broonie@...nel.org, robimarko@...il.com, quic_gurus@...cinc.com,
        bhupesh.sharma@...aro.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-mmc@...r.kernel.org,
        linux-gpio@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 09/10] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board
 support

On 30/01/2023 12:56, Kathiravan Thirumoorthy wrote:
>>>> +        sdhc: mmc@...4000 {
>>>> +            compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
>>>> +            reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>>>> +
>>>> +            interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
>>>> +            interrupt-names = "hc_irq", "pwr_irq";
>>>> +
>>>> +            clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>>>> +                 <&gcc GCC_SDCC1_APPS_CLK>,
>>>> +                 <&xo_board>;
>>>> +            clock-names = "iface", "core", "xo";
>>>> +            mmc-ddr-1_8v;
>>>> +            mmc-hs200-1_8v;
>>>> +            max-frequency = <192000000>;
>>> As Krzysztof pointed out, this one should go.
>>
>>
>> Ack.
> 
> Krzysztof & Konrad,
> 
> These are the properties of the SDHC controller present in the SoC. So I 
> think no need to move out these properties to board DTS. Please let me 
> know if my understanding is otherwise.

Usually max frequency of SDHC controller is depending on the board, so
no, it is not a property of SoC. The same with type of attached memory.


Best regards,
Krzysztof