linux-kernel - Re: [PATCH V2 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 1 Feb 2023 11:10:19 +0530
From:   Kathiravan T <quic_kathirav@...cinc.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <linus.walleij@...aro.org>,
        <catalin.marinas@....com>, <will@...nel.org>,
        <shawnguo@...nel.org>, <arnd@...db.de>,
        <dmitry.baryshkov@...aro.org>, <marcel.ziswiler@...adex.com>,
        <nfraprado@...labora.com>, <robimarko@...il.com>,
        <quic_gurus@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH V2 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board
 support


On 2/1/2023 12:56 AM, Krzysztof Kozlowski wrote:
> On 30/01/2023 12:47, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@...cinc.com>
>>
>> Add initial device tree support for the Qualcomm IPQ5332 SoC and
>> MI01.2 board.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@...cinc.com>
>
>> +		sdhc: mmc@...4000 {
>> +			compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
>> +			reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>> +
>> +			interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "hc_irq", "pwr_irq";
>> +
>> +			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>> +				 <&gcc GCC_SDCC1_APPS_CLK>,
>> +				 <&xo_board>;
>> +			clock-names = "iface", "core", "xo";
>> +			mmc-ddr-1_8v;
>> +			mmc-hs200-1_8v;
> No, our discussion did not finish. These are not properties of the SoC
> in most cases. Why do you say there are part of the SoC? Is your SoC
> coming with the same memory? Memory embedded in the SoC, not in the
> board? If yes, the status is incorrect.


Thanks. Got your point, will move the below properties to the board DTS 
in V3.

mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <192000000>;
bus-width = <4>;


>
>> +			max-frequency = <192000000>;
> Same
>
>
> Best regards,
> Krzysztof
>