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Message-ID: <038b0f5a-5be1-bb90-80f0-29203ad7c0f0@quicinc.com>
Date: Wed, 1 Feb 2023 11:07:43 +0530
From: Kathiravan T <quic_kathirav@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>, <agross@...nel.org>,
<andersson@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <linus.walleij@...aro.org>,
<catalin.marinas@....com>, <will@...nel.org>,
<shawnguo@...nel.org>, <arnd@...db.de>,
<dmitry.baryshkov@...aro.org>, <marcel.ziswiler@...adex.com>,
<nfraprado@...labora.com>, <robimarko@...il.com>,
<quic_gurus@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH V2 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board
support
On 1/30/2023 5:55 PM, Konrad Dybcio wrote:
>
> On 30.01.2023 12:47, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@...cinc.com>
>>
>> Add initial device tree support for the Qualcomm IPQ5332 SoC and
>> MI01.2 board.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@...cinc.com>
>> ---
> [...]
>
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + tz_mem: tz@...00000 {
>> + no-map;
>> + reg = <0x0 0x4a600000 0x0 0x200000>;
> reg should come before no-map
Ack. Will fix it in V3.
>
>
>> + };
>> + };
>> +
>> + soc@0 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0 0xffffffff>;
>> +
>> + tlmm: pinctrl@...0000 {
>> + compatible = "qcom,ipq5332-tlmm";
>> + reg = <0x01000000 0x300000>;
>> + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 53>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + serial_0_pins: serial0-state {
>> + pins = "gpio18", "gpio19";
>> + function = "blsp0_uart0";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + gcc: clock-controller@...0000 {
>> + compatible = "qcom,ipq5332-gcc";
>> + reg = <0x01800000 0x80000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + clock-names = "xo",
>> + "sleep_clk",
>> + "pcie_2lane_phy_pipe_clk",
>> + "pcie_2lane_phy_pipe_clk_x1",
>> + "usb_pcie_wrapper_pipe_clk";
>> + clocks = <&xo_board>,
>> + <&sleep_clk>,
>> + <0>,
>> + <0>,
>> + <0>;
>> + };
>> +
>> + sdhc: mmc@...4000 {
>> + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
>> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>> +
>> + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hc_irq", "pwr_irq";
>> +
>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>> + <&gcc GCC_SDCC1_APPS_CLK>,
>> + <&xo_board>;
>> + clock-names = "iface", "core", "xo";
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + max-frequency = <192000000>;
>> + bus-width = <4>;
>> + status = "disabled";
>> + };
>> +
>> + blsp1_uart0: serial@...f000 {
>> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> + reg = <0x078af000 0x200>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
>> + <&gcc GCC_BLSP1_AHB_CLK>;
>> + clock-names = "core", "iface";
>> + status = "disabled";
>> + };
>> +
>> + intc: interrupt-controller@...0000 {
>> + compatible = "qcom,msm-qgic2";
>> + reg = <0x0b000000 0x1000>, /* GICD */
>> + <0x0b002000 0x1000>, /* GICC */
>> + <0x0b001000 0x1000>, /* GICH */
>> + <0x0b004000 0x1000>; /* GICV */
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x0b00c000 0x3000>;
>> +
>> + v2m0: v2m@0 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00000000 0xffd>;
>> + msi-controller;
>> + };
>> +
>> + v2m1: v2m@1 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00001000 0xffd>;
> The unit address does not match the address part of the reg
> property, dtbs_check will not succeed..
Thanks, will update the node name accordingly in V3. AFAIR, I didn't see
any dtbs_check warning. Let me cross check it again.
>
> The rest lgtm
Thanks a lot for the review!
>
> Konrad
>> + msi-controller;
>> + };
>> +
>> + v2m2: v2m@2 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00002000 0xffd>;
>> + msi-controller;
>> + };
>> + };
>> +
>> + timer@...0000 {
>> + compatible = "arm,armv7-timer-mem";
>> + reg = <0x0b120000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + frame@...0000 {
>> + reg = <0x0b121000 0x1000>,
>> + <0x0b122000 0x1000>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + frame-number = <0>;
>> + };
>> +
>> + frame@...3000 {
>> + reg = <0x0b123000 0x1000>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + frame-number = <1>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...4000 {
>> + reg = <0x0b124000 0x1000>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + frame-number = <2>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...5000 {
>> + reg = <0x0b125000 0x1000>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + frame-number = <3>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...6000 {
>> + reg = <0x0b126000 0x1000>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + frame-number = <4>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...7000 {
>> + reg = <0x0b127000 0x1000>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + frame-number = <5>;
>> + status = "disabled";
>> + };
>> +
>> + frame@...8000 {
>> + reg = <0x0b128000 0x1000>;
>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> + frame-number = <6>;
>> + status = "disabled";
>> + };
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +};
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