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Message-ID: <20230208155720.GA2397622@hu-bjorande-lv.qualcomm.com>
Date: Wed, 8 Feb 2023 07:57:20 -0800
From: Bjorn Andersson <quic_bjorande@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>
CC: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 2/4] arm64: dts: qcom: sc8280xp-crd: Introduce pmic_glink
On Wed, Feb 08, 2023 at 09:14:46AM +0100, Konrad Dybcio wrote:
>
>
> On 8.02.2023 04:46, Bjorn Andersson wrote:
> > From: Bjorn Andersson <bjorn.andersson@...aro.org>
> >
> > The SC8280XP CRD control over battery management and its two USB Type-C
> > port using pmic_glink and two GPIO-based SBU muxes.
> >
> > Enable the two DisplayPort instances, GPIO SBU mux instance and
> > pmic_glink with the two connectors on the CRD.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> > Signed-off-by: Bjorn Andersson <quic_bjorande@...cinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 191 +++++++++++++++++++++-
> > 1 file changed, 189 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > index 3f116a879e22..35b63c3962f0 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > @@ -36,6 +36,77 @@ chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + pmic-glink {
> > + compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + connector@0 {
> > + compatible = "usb-c-connector";
> > + reg = <0>;
> > + power-role = "dual";
> > + data-role = "dual";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> Add a newline between the last propreties and first subnodes, please.
>
> > + port@0 {
> > + reg = <0>;
> > + pmic_glink_con0_hs: endpoint {
> > + remote-endpoint = <&usb_0_role_switch>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + pmic_glink_con0_ss: endpoint {
> > + remote-endpoint = <&mdss0_dp0_out>;
> > + };
> > + };
> > +
> > + port@2 {
> > + reg = <2>;
> > + pmic_glink_con0_sbu: endpoint {
> > + remote-endpoint = <&usb0_sbu_mux>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + connector@1 {
> > + compatible = "usb-c-connector";
> > + reg = <1>;
> > + power-role = "dual";
> > + data-role = "dual";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + port@0 {
> > + reg = <0>;
> > + pmic_glink_con1_hs: endpoint {
> > + remote-endpoint = <&usb_1_role_switch>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + pmic_glink_con1_ss: endpoint {
> > + remote-endpoint = <&mdss0_dp1_out>;
> > + };
> > + };
> > +
> > + port@2 {
> > + reg = <2>;
> > + pmic_glink_con1_sbu: endpoint {
> > + remote-endpoint = <&usb1_sbu_mux>;
> > + };
> > + };
> > + };
> > + };
> > + };
> > +
> > vreg_edp_3p3: regulator-edp-3p3 {
> > compatible = "regulator-fixed";
> >
> > @@ -139,6 +210,46 @@ linux,cma {
> > linux,cma-default;
> > };
> > };
> > +
> > + usb0-sbu-mux {
> > + compatible = "pericom,pi3usb102", "gpio-sbu-mux";
> > +
> > + enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
> > + select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&usb0_sbu_default>;
> > +
> > + mode-switch;
> > + orientation-switch;
> > + svid = /bits/ 16 <0xff01>;
> > +
> > + port {
> > + usb0_sbu_mux: endpoint {
> > + remote-endpoint = <&pmic_glink_con0_sbu>;
> > + };
> > + };
> > + };
> > +
> > + usb1-sbu-mux {
> > + compatible = "pericom,pi3usb102", "gpio-sbu-mux";
> > +
> > + enable-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
> > + select-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&usb1_sbu_default>;
> > +
> > + mode-switch;
> > + orientation-switch;
> > + svid = /bits/ 16 <0xff01>;
> > +
> > + port {
> > + usb1_sbu_mux: endpoint {
> > + remote-endpoint = <&pmic_glink_con1_sbu>;
> > + };
> > + };
> > + };
> > };
> >
> > &apps_rsc {
> > @@ -262,6 +373,36 @@ &mdss0 {
> > status = "okay";
> > };
> >
> > +&mdss0_dp0 {
> > + status = "okay";
> > +
> > + data-lanes = <0 1>;
> Status last; is this really only 2 lanes?
>
> > +
> > + ports {
> > + port@1 {
> > + reg = <1>;
> > + mdss0_dp0_out: endpoint {
> > + remote-endpoint = <&pmic_glink_con0_ss>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&mdss0_dp1 {
> > + status = "okay";
> > +
> > + data-lanes = <0 1>;
> Ditto
>
> > +
> > + ports {
> > + port@1 {
> > + reg = <1>;
> > + mdss0_dp1_out: endpoint {
> > + remote-endpoint = <&pmic_glink_con1_ss>;
> > + };
> > + };
> > + };
> > +};
> > +
> > &mdss0_dp3 {
> > compatible = "qcom,sc8280xp-edp";
> > /delete-property/ #sound-dai-cells;
> > @@ -480,8 +621,13 @@ &usb_0 {
> > };
> >
> > &usb_0_dwc3 {
> > - /* TODO: Define USB-C connector properly */
> > dr_mode = "host";
> > +
> > + port {
> > + usb_0_role_switch: endpoint {
> > + remote-endpoint = <&pmic_glink_con0_hs>;
> > + };
> This should be defined in the SoC DTSI, it's a standard dwc3 binding
> with usb HS / SS / SBU ports. Especially since we can feed the endpoint
> from any device now, as pmic-glink should work everywhere.
>
The sa8295p/sa8540p boards, derived from sc8280xp does not implement
pmic_glink, so it seems moving this to the soc.dtsi would be messy.
> Or /omit-if-no-ref/, I suppose.
>
Or you're saying I should put the skeleton of the port definition in the
soc.dtsi and then fill it out the remote-endpoint here; and mark it
omit-if-no-ref to avoid binding warnings?
> > + };
> > };
> >
> > &usb_0_hsphy {
> > @@ -504,8 +650,13 @@ &usb_1 {
> > };
> >
> > &usb_1_dwc3 {
> > - /* TODO: Define USB-C connector properly */
> > dr_mode = "host";
> > +
> > + port {
> > + usb_1_role_switch: endpoint {
> > + remote-endpoint = <&pmic_glink_con1_hs>;
> > + };
> > + };
> > };
> >
> > &usb_1_hsphy {
> > @@ -709,4 +860,40 @@ reset-n-pins {
> > drive-strength = <16>;
> > };
> > };
> > +
> > + usb0_sbu_default: usb0-sbu-state {
> > + oe-n-pins {
> > + pins = "gpio101";
> > + function = "gpio";
> No drive-strength/bias/i/o?
>
Seems like a reasonable ask...
Thanks,
Bjorn
> Konrad
> > + };
> > +
> > + sel-pins {
> > + pins = "gpio164";
> > + function = "gpio";
> > + };
> > +
> > + mode-pins {
> > + pins = "gpio167";
> > + function = "gpio";
> > + output-high;
> > + };
> > + };
> > +
> > + usb1_sbu_default: usb1-sbu-state {
> > + oe-n-pins {
> > + pins = "gpio48";
> > + function = "gpio";
> > + };
> > +
> > + sel-pins {
> > + pins = "gpio47";
> > + function = "gpio";
> > + };
> > +
> > + mode-pins {
> > + pins = "gpio50";
> > + function = "gpio";
> > + output-high;
> > + };
> > + };
> > };
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