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Message-ID: <Y+T5cF4d667RhrJp@gerhold.net>
Date: Thu, 9 Feb 2023 14:47:28 +0100
From: Stephan Gerhold <stephan@...hold.net>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Cc: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
djakov@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-arm-msm@...r.kernel.org,
linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, benl@...areup.com,
shawn.guo@...aro.org, fabien.parent@...aro.org, leo.yan@...aro.org,
dmitry.baryshkov@...aro.org, Jun Nie <jun.nie@...aro.org>,
James Willcox <jwillcox@...areup.com>,
Joseph Gates <jgates@...areup.com>,
Max Chen <mchen@...areup.com>, Zac Crosby <zac@...areup.com>,
Vincent Knecht <vincent.knecht@...loo.org>
Subject: Re: [PATCH v5 2/5] arm64: dts: qcom: Add msm8939 SoC
On Mon, Feb 06, 2023 at 01:23:33AM +0000, Bryan O'Donoghue wrote:
> Add msm8939 a derivative SoC of msm8916. This SoC contains a number of key
> differences to msm8916.
>
> - big.LITTLE Octa Core - quad 1.5GHz + quad 1.0GHz
> - DRAM 1x800 LPDDR3
> - Camera 4+4 lane CSI
> - Venus @ 1080p60 HEVC
> - DSI x 2
> - Adreno A405
> - WiFi wcn3660/wcn3680b 802.11ac
>
> Co-developed-by: Shawn Guo <shawn.guo@...aro.org>
> Signed-off-by: Shawn Guo <shawn.guo@...aro.org>
> Co-developed-by: Jun Nie <jun.nie@...aro.org>
> Signed-off-by: Jun Nie <jun.nie@...aro.org>
> Co-developed-by: Benjamin Li <benl@...areup.com>
> Signed-off-by: Benjamin Li <benl@...areup.com>
> Co-developed-by: James Willcox <jwillcox@...areup.com>
> Signed-off-by: James Willcox <jwillcox@...areup.com>
> Co-developed-by: Leo Yan <leo.yan@...aro.org>
> Signed-off-by: Leo Yan <leo.yan@...aro.org>
> Co-developed-by: Joseph Gates <jgates@...areup.com>
> Signed-off-by: Joseph Gates <jgates@...areup.com>
> Co-developed-by: Max Chen <mchen@...areup.com>
> Signed-off-by: Max Chen <mchen@...areup.com>
> Co-developed-by: Zac Crosby <zac@...areup.com>
> Signed-off-by: Zac Crosby <zac@...areup.com>
> Co-developed-by: Vincent Knecht <vincent.knecht@...loo.org>
> Signed-off-by: Vincent Knecht <vincent.knecht@...loo.org>
> Co-developed-by: Stephan Gerhold <stephan@...hold.net>
> Signed-off-by: Stephan Gerhold <stephan@...hold.net>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/msm8939.dtsi | 2344 +++++++++++++++++++++++++
> 1 file changed, 2344 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/msm8939.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
> new file mode 100644
> index 0000000000000..17327513a5698
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
> @@ -0,0 +1,2344 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2020-2023, Linaro Limited
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-msm8939.h>
> +#include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/interconnect/qcom,msm8939.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/reset/qcom,gcc-msm8939.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + /*
> + * Stock LK wants address-cells/size-cells = 2
> + * A number of our drivers want address/size cells = 1
> + * hence the disparity between top-level and /soc below.
> + */
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@100 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "spin-table";
> + reg = <0x100>;
> + next-level-cache = <&L2_1>;
> + power-domains = <&vreg_cpr_stub>;
> + power-domain-names = "cpr";
IMHO there are still no compelling arguments for adding this dummy stub
here, aside from fixing a non-critical DT schema warning that is
obviously wrong and is being fixed in [1]. But I guess I have made my
point and you have made yours so I'll leave it up to Bjorn to decide.
[1]: https://lore.kernel.org/linux-arm-msm/20230208153913.24436-2-ansuelsmth@gmail.com/
Otherwise I just have some more nitpicks and one critical issue:
The timer interrupt numbers are still wrong.
> + [...]
> + tsens: thermal-sensor@...000 {
> + compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
> + reg = <0x004a9000 0x1000>, /* TM */
> + <0x004a8000 0x1000>; /* SROT */
> + nvmem-cells = <&tsens_caldata>;
> + nvmem-cell-names = "calib";
> + #qcom,sensors = <10>;
> + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "uplow";
> + #thermal-sensor-cells = <1>;
> + };
"thermal/drivers/tsens: Drop single-cell code for msm8939" [2] is in
linux-next now so you need to convert this to use multiple nvmem-cells.
[2]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=dfadb4599ab0206935d5f14975b5e8112492b29c
> + [...]
> + mdss: display-subsystem@...0000 {
> + compatible = "qcom,mdss";
> + reg = <0x01a00000 0x1000>,
> + <0x01ac8000 0x3000>;
> + reg-names = "mdss_phys", "vbif_phys";
> +
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> +
> + clocks = <&gcc GCC_MDSS_AHB_CLK>,
> + <&gcc GCC_MDSS_AXI_CLK>,
> + <&gcc GCC_MDSS_VSYNC_CLK>;
> + clock-names = "iface",
> + "bus",
> + "vsync";
> +
> + power-domains = <&gcc MDSS_GDSC>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> + ranges;
Please disable this by default similar to 5f36d633c214 ("arm64: dts:
qcom: Disable MDSS by default for 8916/8016 devices") for consistency
with MSM8916.
> + [...]
> + apps_iommu: iommu@...0000 {
> + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
> + reg = <0x01ef0000 0x3000>;
> + ranges = <0 0x1e20000 0x40000>;
0x01e20000 (pad to 8 digits)
> + [...]
> + usb: usb@...9000 {
> + compatible = "qcom,ci-hdrc";
> + reg = <0x078d9000 0x200>,
> + <0x078d9200 0x200>;
> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_USB_HS_AHB_CLK>,
> + <&gcc GCC_USB_HS_SYSTEM_CLK>;
> + clock-names = "iface", "core";
> + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
> + assigned-clock-rates = <80000000>;
> + resets = <&gcc GCC_USB_HS_BCR>;
> + reset-names = "core";
> + #reset-cells = <1>;
> + phy_type = "ulpi";
> + dr_mode = "otg";
> + ahb-burst-config = <0>;
> + phy-names = "usb-phy";
> + phys = <&usb_hs_phy>;
> + status = "disabled";
> +
> + ulpi {
> + usb_hs_phy: phy {
> + compatible = "qcom,usb-hs-phy-msm8916",
> + "qcom,usb-hs-phy";
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> + clock-names = "ref", "sleep";
> + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
> + reset-names = "phy", "por";
> + #phy-cells = <0>;
> + qcom,init-seq = /bits/ 8 <0x0 0x44
> + 0x1 0x6b 0x2 0x24 0x3 0x13>;
Should be formatted in pairs, see commit 640e71aac554c ("arm64: dts:
qcom: msm8916: improve usb hs node formating").
> + [...]
> + timer@...0000 {
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x0b020000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + frame@...1000 {
> + reg = <0x0b021000 0x1000>,
> + <0x0b022000 0x1000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <0>;
> + };
These timer interrupts are still wrong like mentioned in v3:
https://lore.kernel.org/linux-arm-msm/Y8fC%2FGCHfENQmBNC@gerhold.net/
> + [...]
> + pronto: remoteproc@...4000 {
> + compatible = "qcom,pronto-v2-pil", "qcom,pronto";
> + reg = <0x0a204000 0x2000>,
> + <0x0a202000 0x1000>,
> + <0x0a21b000 0x3000>;
> + reg-names = "ccu", "dxe", "pmu";
> +
> + interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
&intc GIC_SPI 149
Thanks,
Stephan
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