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Message-ID: <CAAhV-H4VqA0HmrG1B_NNsX=7Stnun1B_TCQiKa-3h1Y_Y1JqOA@mail.gmail.com>
Date: Fri, 10 Feb 2023 17:04:55 +0800
From: Huacai Chen <chenhuacai@...nel.org>
To: Youling Tang <tangyouling@...ngson.cn>
Cc: Xi Ruoyao <xry111@...111.site>, Jinyang He <hejinyang@...ngson.cn>,
Xuerui Wang <kernel@...0n.name>, loongarch@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/5] LoongArch: Use la.pcrel instead of la.abs when
it's trivially possible
Hi, Youling,
On Fri, Feb 10, 2023 at 4:47 PM Youling Tang <tangyouling@...ngson.cn> wrote:
>
> From: Xi Ruoyao <xry111@...111.site>
>
> Let's start to kill la.abs inpreparation for the subsequent support of the
> PIE kernel.
>
> Signed-off-by: Xi Ruoyao <xry111@...111.site>
> ---
> arch/loongarch/include/asm/stackframe.h | 2 +-
> arch/loongarch/include/asm/uaccess.h | 1 -
> arch/loongarch/kernel/entry.S | 2 +-
> arch/loongarch/kernel/head.S | 2 +-
> arch/loongarch/mm/tlbex.S | 3 +--
> 5 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/stackframe.h b/arch/loongarch/include/asm/stackframe.h
> index 4ca953062b5b..7deb043ce387 100644
> --- a/arch/loongarch/include/asm/stackframe.h
> +++ b/arch/loongarch/include/asm/stackframe.h
> @@ -90,7 +90,7 @@
> .endm
>
> .macro set_saved_sp stackp temp temp2
> - la.abs \temp, kernelsp
> + la.pcrel \temp, kernelsp
> #ifdef CONFIG_SMP
> LONG_ADD \temp, \temp, u0
> #endif
> diff --git a/arch/loongarch/include/asm/uaccess.h b/arch/loongarch/include/asm/uaccess.h
> index 255899d4a7c3..0d22991ae430 100644
> --- a/arch/loongarch/include/asm/uaccess.h
> +++ b/arch/loongarch/include/asm/uaccess.h
> @@ -22,7 +22,6 @@
> extern u64 __ua_limit;
>
> #define __UA_ADDR ".dword"
> -#define __UA_LA "la.abs"
> #define __UA_LIMIT __ua_limit
>
> /*
> diff --git a/arch/loongarch/kernel/entry.S b/arch/loongarch/kernel/entry.S
> index d53b631c9022..2566977f2f68 100644
> --- a/arch/loongarch/kernel/entry.S
> +++ b/arch/loongarch/kernel/entry.S
> @@ -20,7 +20,7 @@
> .align 5
> SYM_FUNC_START(handle_syscall)
> csrrd t0, PERCPU_BASE_KS
> - la.abs t1, kernelsp
> + la.pcrel t1, kernelsp
Retab the whole function to align the first parameter, please.
Huacai
> add.d t1, t1, t0
> move t2, sp
> ld.d sp, t1, 0
> diff --git a/arch/loongarch/kernel/head.S b/arch/loongarch/kernel/head.S
> index 57bada6b4e93..aa6181714ec3 100644
> --- a/arch/loongarch/kernel/head.S
> +++ b/arch/loongarch/kernel/head.S
> @@ -117,7 +117,7 @@ SYM_CODE_START(smpboot_entry)
> li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
> csrwr t0, LOONGARCH_CSR_EUEN
>
> - la.abs t0, cpuboot_data
> + la.pcrel t0, cpuboot_data
> ld.d sp, t0, CPU_BOOT_STACK
> ld.d tp, t0, CPU_BOOT_TINFO
>
> diff --git a/arch/loongarch/mm/tlbex.S b/arch/loongarch/mm/tlbex.S
> index 58781c6e4191..3dd2a9615cd9 100644
> --- a/arch/loongarch/mm/tlbex.S
> +++ b/arch/loongarch/mm/tlbex.S
> @@ -24,8 +24,7 @@
> move a0, sp
> REG_S a2, sp, PT_BVADDR
> li.w a1, \write
> - la.abs t0, do_page_fault
> - jirl ra, t0, 0
> + bl do_page_fault
> RESTORE_ALL_AND_RET
> SYM_FUNC_END(tlb_do_page_fault_\write)
> .endm
> --
> 2.37.3
>
>
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