linux-kernel - Re: [PATCH v4 10/12] net: pcs: add driver for MediaTek SGMII PCS

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Message-ID: <Y+ePrq4pTLOuTNIc@shell.armlinux.org.uk>
Date:   Sat, 11 Feb 2023 12:53:02 +0000
From:   "Russell King (Oracle)" <linux@...linux.org.uk>
To:     Daniel Golle <daniel@...rotopia.org>
Cc:     netdev@...r.kernel.org, linux-mediatek@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Heiner Kallweit <hkallweit1@...il.com>,
        Lorenzo Bianconi <lorenzo@...nel.org>,
        Mark Lee <Mark-MC.Lee@...iatek.com>,
        John Crispin <john@...ozen.org>, Felix Fietkau <nbd@....name>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        DENG Qingfang <dqfext@...il.com>,
        Landen Chao <Landen.Chao@...iatek.com>,
        Sean Wang <sean.wang@...iatek.com>,
        Paolo Abeni <pabeni@...hat.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Eric Dumazet <edumazet@...gle.com>,
        "David S. Miller" <davem@...emloft.net>,
        Vladimir Oltean <olteanv@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Andrew Lunn <andrew@...n.ch>,
        Jianhui Zhao <zhaojh329@...il.com>,
        Bjørn Mork <bjorn@...k.no>
Subject: Re: [PATCH v4 10/12] net: pcs: add driver for MediaTek SGMII PCS

Hi Daniel,

On Fri, Feb 10, 2023 at 11:39:59PM +0000, Daniel Golle wrote:
> +	if (mpcs->interface != interface) {
> +		/* PHYA power down */
> +		regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
> +				   SGMII_PHYA_PWD, SGMII_PHYA_PWD);
> +
> +		/* Reset SGMII PCS state */
> +		regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
> +				   SGMII_SW_RESET, SGMII_SW_RESET);
> +
> +		if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
> +			regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
> +					   SGMII_PN_SWAP_MASK,
> +					   SGMII_PN_SWAP_TX_RX);
> +
> +		if (interface == PHY_INTERFACE_MODE_2500BASEX)
> +			rgc3 = RG_PHY_SPEED_3_125G;
> +		else
> +			rgc3 = 0;
> +
> +		/* Configure the underlying interface speed */
> +		regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
> +				   RG_PHY_SPEED_MASK, rgc3);
> +
> +		/* Setup the link timer and QPHY power up inside SGMIISYS */
> +		link_timer = phylink_get_link_timer_ns(interface);
> +		if (link_timer < 0)
> +			return link_timer;

The change in patch 7 needs to be propagated to this patch (moving this
to the beginning of this block of code.)

Otherwise, LGTM. Thanks.

-- 
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