linux-kernel - Re: [PATCH] irqchip/gic-v3-its: remove the shareability of ITS

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Date:   Mon, 13 Feb 2023 15:30:08 +0800
From:   Harry Song <jundongsong1@...il.com>
To:     Marc Zyngier <maz@...nel.org>
Cc:     Sebastian Reichel <sebastian.reichel@...labora.com>,
        tglx@...utronix.de, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] irqchip/gic-v3-its: remove the shareability of ITS

On Fri, Dec 9, 2022 at 9:37 PM Harry Song <jundongsong1@...il.com> wrote:
>
> Thank you again.
>
> Harry
>
> On Fri, Dec 9, 2022 at 7:13 PM Marc Zyngier <maz@...nel.org> wrote:
> >
> > On Fri, 09 Dec 2022 03:34:21 +0000,
> > Harry Song <jundongsong1@...il.com> wrote:
> > >
> > > Thank you for your reply. I know these two links.
> > > My email is to ask about the root cause of this bug.
> > >
> > > I would like to know whether the driver design of ITS requires that
> > > the CPU and ITS must be in a shared domain. Such as using CCI in
> > > chips;
> >
> > This problem has nothing to do with CCI or coherency. It has to do
> > with how the GIC is plugged in the interconnect and what attributes it
> > advertises.

This problem has nothing to do with CCI or coherency ??

Now , I have a question about this sentence：
If CCI is not used, how does the hardware realize the interconnection
between GIC-600 and cache?
If CCI is not used, our hardware colleagues said that the internal ITS
of the GIC-600 sends out operations with cache attributes (Inner/Outer
Shareable),
and there is no way to be captured by the cache and directly enter the
DDR. How does arm realize the interconnection between GIC-600 and
cache without CCI?

Waiting for your reply.

Harry Song.

> >
> >         M.
> >
>
> Wow, that's a great link:
> https://lore.kernel.org/lkml/878s5i2qyw.wl-maz@kernel.org/
>
> Many thanks for your detailed reply.
> I got the answer I wanted to know, That was very helpful.
>
> > --
> > Without deviation from the norm, progress is not possible.
>
> Thank you again,
> Harry