linux-kernel - Re: [PATCH] irqchip/gic-v3-its: remove the shareability of ITS

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Message-ID: <86357ayncj.wl-maz@kernel.org>
Date:   Mon, 13 Feb 2023 08:35:24 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Harry Song <jundongsong1@...il.com>
Cc:     Sebastian Reichel <sebastian.reichel@...labora.com>,
        tglx@...utronix.de, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] irqchip/gic-v3-its: remove the shareability of ITS

On Mon, 13 Feb 2023 07:30:08 +0000,
Harry Song <jundongsong1@...il.com> wrote:
> 
> On Fri, Dec 9, 2022 at 9:37 PM Harry Song <jundongsong1@...il.com> wrote:
> >
> > Thank you again.
> >
> > Harry
> >
> > On Fri, Dec 9, 2022 at 7:13 PM Marc Zyngier <maz@...nel.org> wrote:
> > >
> > > On Fri, 09 Dec 2022 03:34:21 +0000,
> > > Harry Song <jundongsong1@...il.com> wrote:
> > > >
> > > > Thank you for your reply. I know these two links.
> > > > My email is to ask about the root cause of this bug.
> > > >
> > > > I would like to know whether the driver design of ITS requires that
> > > > the CPU and ITS must be in a shared domain. Such as using CCI in
> > > > chips;
> > >
> > > This problem has nothing to do with CCI or coherency. It has to do
> > > with how the GIC is plugged in the interconnect and what attributes it
> > > advertises.
> 
> This problem has nothing to do with CCI or coherency ??
>
> Now , I have a question about this sentence：
> If CCI is not used, how does the hardware realize the interconnection
> between GIC-600 and cache?
> If CCI is not used, our hardware colleagues said that the internal ITS
> of the GIC-600 sends out operations with cache attributes (Inner/Outer
> Shareable),
> and there is no way to be captured by the cache and directly enter the
> DDR. How does arm realize the interconnection between GIC-600 and
> cache without CCI?

This is becoming tedious.

Why do you need things to be cacheable/shareable? The HW doesn't need
it, and the SW doesn't need it either.

All that SW needs is to be told *how* the HW behaves, and it relies on
the GIC to tell it by not accepting configurations it cannot support.
That's all. This is all described in the thread I pointed you to last
year.

If your HW is accepting configurations it cannot deal with, then it is
a bug. You can work around it (again see the thread I pointed you to),
or you can continue to moan about it.

But I'm not interested in arguing further about this.

Also, for ARM integration problems, please contact the ARM technical
support. I'm here for Linux, and nothing else.

	M.

-- 
Without deviation from the norm, progress is not possible.