linux-kernel - Re: [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for sa8775p-ride

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Date:   Wed, 15 Feb 2023 12:36:45 +0530
From:   Shazad Hussain <quic_shazhuss@...cinc.com>
To:     Bartosz Golaszewski <brgl@...ev.pl>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC:     <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed
 UART for sa8775p-ride



On 2/14/2023 9:27 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> 
> Add the serial port connected to the GNSS on sa8775p-ride.
> 

Same here, this is for BT HS UART.

-Shazad

> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> ---
>   arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++
>   arch/arm64/boot/dts/qcom/sa8775p.dtsi     | 17 ++++++++++++
>   2 files changed, 51 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> index d01ca3a9ee37..9aee6e4c1ba1 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -13,6 +13,7 @@ / {
>   
>   	aliases {
>   		serial0 = &uart10;
> +		serial1 = &uart17;
>   		i2c18 = &i2c18;
>   		spi16 = &spi16;
>   	};
> @@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state {
>   		drive-strength = <2>;
>   		bias-pull-up;
>   	};
> +
> +	qup_uart17_cts: qup-uart17-cts-state {
> +		pins = "gpio91";
> +		function = "qup2_se3";
> +		bias-disable;
> +	};
> +
> +	qup_uart17_rts: qup0_uart17_rts-state {
> +		pins = "gpio92";
> +		function = "qup2_se3";
> +		bias-pull-down;
> +	};
> +
> +	qup_uart17_tx: qup0_uart17_tx-state {
> +		pins = "gpio93";
> +		function = "qup2_se3";
> +		bias-pull-up;
> +	};
> +
> +	qup_uart17_rx: qup0_uart17_rx-state {
> +		pins = "gpio94";
> +		function = "qup2_se3";
> +		bias-pull-down;
> +	};
>   };
>   
>   &uart10 {
> @@ -75,6 +100,15 @@ &uart10 {
>   	status = "okay";
>   };
>   
> +&uart17 {
> +	pinctrl-0 = <&qup_uart17_cts>,
> +		    <&qup_uart17_rts>,
> +		    <&qup_uart17_tx>,
> +		    <&qup_uart17_rx>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
>   &xo_board_clk {
>   	clock-frequency = <38400000>;
>   };
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 1abb545ff4f4..b009e1100c0a 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -524,6 +524,23 @@ &config_noc SLAVE_QUP_2 0>,
>   				status = "disabled";
>   			};
>   
> +			uart17: serial@...000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0x0 0x88c000 0x0 0x4000>;
> +				interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> +				clock-names = "se";
> +				interconnects = <&clk_virt MASTER_QUP_CORE_2 0
> +						 &clk_virt SLAVE_QUP_CORE_2 0>,
> +						<&gem_noc MASTER_APPSS_PROC 0
> +						 &config_noc SLAVE_QUP_2 0>;
> +				interconnect-names = "qup-core",
> +						     "qup-config";
> +				power-domains = <&rpmhpd SA8775P_CX>;
> +				status = "disabled";
> +			};
> +
>   			i2c18: i2c@...000 {
>   				compatible = "qcom,geni-i2c";
>   				reg = <0x0 0x890000 0x0 0x4000>;