linux-kernel - Re: [PATCH 2/2] mips: dts: ralink: mt7621: add port@5 as CPU port

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Message-ID: <20230217110306.GB7138@alpha.franken.de>
Date:   Fri, 17 Feb 2023 12:03:06 +0100
From:   Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To:     arinc9.unal@...il.com
Cc:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Cercueil <paul@...pouillou.net>,
        Matthias Brugger <matthias.bgg@...il.com>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        Sergio Paracuellos <sergio.paracuellos@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Arınç ÜNAL <arinc.unal@...nc9.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        devicetree@...r.kernel.org, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, erkin.bozoglu@...ont.com
Subject: Re: [PATCH 2/2] mips: dts: ralink: mt7621: add port@5 as CPU port

On Sat, Feb 11, 2023 at 01:49:15PM +0300, arinc9.unal@...il.com wrote:
> From: Arınç ÜNAL <arinc.unal@...nc9.com>
> 
> On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is
> connected to the second MAC of the SoC as a CPU port. Add the port and set
> up the second MAC on the bindings. Revert PHY muxing on GB-PC1.
> 
> There's an external PHY connected to the second MAC of the SoC on GB-PC2,
> therefore, disable port@5 for this device.
> 
> Signed-off-by: Arınç ÜNAL <arinc.unal@...nc9.com>
> ---
>  .../boot/dts/ralink/mt7621-gnubee-gb-pc1.dts  | 16 +++++-----------
>  .../boot/dts/ralink/mt7621-gnubee-gb-pc2.dts  |  9 ++++++++-
>  arch/mips/boot/dts/ralink/mt7621.dtsi         | 19 ++++++++++++++++++-
>  3 files changed, 31 insertions(+), 13 deletions(-)

applied to mips-next.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]