linux-kernel - [PATCH v3 1/2] dt-bindings: watchdog: Add watchdog for StarFive JH7110

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Message-ID: <20230220081926.267695-2-xingyu.wu@starfivetech.com>
Date:   Mon, 20 Feb 2023 16:19:25 +0800
From:   Xingyu Wu <xingyu.wu@...rfivetech.com>
To:     <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-watchdog@...r.kernel.org>,
        Wim Van Sebroeck <wim@...ux-watchdog.org>,
        Guenter Roeck <linux@...ck-us.net>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC:     Rob Herring <robh+dt@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Xingyu Wu <xingyu.wu@...rfivetech.com>,
        Samin Guo <samin.guo@...rfivetech.com>,
        <linux-kernel@...r.kernel.org>, Conor Dooley <conor@...nel.org>
Subject: [PATCH v3 1/2] dt-bindings: watchdog: Add watchdog for StarFive JH7110

Add bindings to describe the watchdog for the StarFive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
---
 .../watchdog/starfive,jh7110-wdt.yaml         | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/watchdog/starfive,jh7110-wdt.yaml

diff --git a/Documentation/devicetree/bindings/watchdog/starfive,jh7110-wdt.yaml b/Documentation/devicetree/bindings/watchdog/starfive,jh7110-wdt.yaml
new file mode 100644
index 000000000000..05ba7069e29a
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/starfive,jh7110-wdt.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/starfive,jh7110-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive Watchdog
+
+maintainers:
+  - Samin Guo <samin.guo@...rfivetech.com>
+  - Xingyu Wu <xingyu.wu@...rfivetech.com>
+
+description:
+  The watchdog is a 32 bit counter and has two timeout phases.
+  At the first phase, the signal of watchdog interrupt output(WDOGINT)
+  will rise when counter is 0. The counter will reload the timeout value.
+  And then, if counter decreases to 0 again and WDOGINT isn't cleared,
+  the watchdog will reset the system unless the watchdog reset is disabled.
+
+allOf:
+  - $ref: watchdog.yaml#
+
+properties:
+  compatible:
+    const: starfive,jh7110-wdt
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: APB clock
+      - description: Core clock
+
+  clock-names:
+    items:
+      - const: apb
+      - const: core
+
+  resets:
+    items:
+      - description: APB reset
+      - description: Core reset
+
+  reset-names:
+    items:
+      - const: apb
+      - const: core
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    watchdog@...70000 {
+        compatible = "starfive,jh7110-wdt";
+        reg = <0x13070000 0x10000>;
+        clocks = <&clk 122>,
+                 <&clk 123>;
+        clock-names = "apb", "core";
+        resets = <&rst 109>,
+                 <&rst 110>;
+        reset-names = "apb", "core";
+    };
-- 
2.25.1