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Message-ID: <348796cc-72d9-4dcf-9f09-4c2aa55cb858@starfivetech.com>
Date: Tue, 21 Feb 2023 10:44:02 +0800
From: William Qiu <william.qiu@...rfivetech.com>
To: Rob Herring <robh@...nel.org>
CC: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-mmc@...r.kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Jaehoon Chung <jh80.chung@...sung.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 4/4] dt-bindings: syscon: Add StarFive syscon doc
On 2023/2/21 7:43, Rob Herring wrote:
> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>>
>> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
>> ---
>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++
>> MAINTAINERS | 5 ++
>> 2 files changed, 56 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..fa4d8522a454
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
>> @@ -0,0 +1,51 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@...rfivetech.com>
>> +
>> +description: |
>> + The StarFive JH7110 SoC system controller provides register information such
>> + as offset, mask and shift to configure related modules such as MMC and PCIe.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - starfive,jh7110-stg-syscon
>> + - starfive,jh7110-sys-syscon
>> + - starfive,jh7110-aon-syscon
>
> Is 'syscon' really part of what the blocks are called? Is just 'stg',
> 'sys' and 'aon' not unique enough?
>
> Rob
Hi Rob,
In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock
controller, so 'syscon' is added to avoid confusion.
Best regards
William
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