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Message-ID: <Y/jqCRAenwbqc1Uu@sirena.org.uk>
Date:   Fri, 24 Feb 2023 16:47:05 +0000
From:   Mark Brown <broonie@...nel.org>
To:     Krishna Yarlagadda <kyarlagadda@...dia.com>
Cc:     linux-spi@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, thierry.reding@...il.com,
        jonathanh@...dia.com, skomatineni@...dia.com, ldewangan@...dia.com
Subject: Re: [PATCH] spi: tegra210-quad: Fix iterator outside loop

On Fri, Feb 24, 2023 at 10:05:13PM +0530, Krishna Yarlagadda wrote:

>  		msg->actual_length += xfer->len;
> +		if (!xfer->cs_change && transfer_phase == DATA_TRANSFER) {
> +			tegra_qspi_transfer_end(spi);
> +			spi_transfer_delay_exec(xfer);
> +		}
>  		transfer_phase++;
>  	}
> -	if (!xfer->cs_change) {
> -		tegra_qspi_transfer_end(spi);
> -		spi_transfer_delay_exec(xfer);
> -	}

This looks like it'll do the wrong thing and do a change on every
transfer if cs_change isn't set?

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