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Message-ID: <DM4PR12MB5769BDB91342A9768207BD84C3A89@DM4PR12MB5769.namprd12.prod.outlook.com>
Date: Fri, 24 Feb 2023 16:50:00 +0000
From: Krishna Yarlagadda <kyarlagadda@...dia.com>
To: Mark Brown <broonie@...nel.org>
CC: "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"thierry.reding@...il.com" <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Sowjanya Komatineni <skomatineni@...dia.com>,
Laxman Dewangan <ldewangan@...dia.com>
Subject: RE: [PATCH] spi: tegra210-quad: Fix iterator outside loop
> -----Original Message-----
> From: Mark Brown <broonie@...nel.org>
> Sent: 24 February 2023 22:17
> To: Krishna Yarlagadda <kyarlagadda@...dia.com>
> Cc: linux-spi@...r.kernel.org; linux-tegra@...r.kernel.org; linux-
> kernel@...r.kernel.org; thierry.reding@...il.com; Jonathan Hunter
> <jonathanh@...dia.com>; Sowjanya Komatineni
> <skomatineni@...dia.com>; Laxman Dewangan <ldewangan@...dia.com>
> Subject: Re: [PATCH] spi: tegra210-quad: Fix iterator outside loop
>
> On Fri, Feb 24, 2023 at 10:05:13PM +0530, Krishna Yarlagadda wrote:
>
> > msg->actual_length += xfer->len;
> > + if (!xfer->cs_change && transfer_phase == DATA_TRANSFER)
> {
> > + tegra_qspi_transfer_end(spi);
> > + spi_transfer_delay_exec(xfer);
> > + }
> > transfer_phase++;
> > }
> > - if (!xfer->cs_change) {
> > - tegra_qspi_transfer_end(spi);
> > - spi_transfer_delay_exec(xfer);
> > - }
>
> This looks like it'll do the wrong thing and do a change on every
> transfer if cs_change isn't set?
This condition is hit only in data phase which is end of message.
KY
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