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Message-ID: <Y/zykfydb+bJ7G2l@spud>
Date: Mon, 27 Feb 2023 18:12:33 +0000
From: Conor Dooley <conor@...nel.org>
To: Hal Feng <hal.feng@...rfivetech.com>
Cc: Emil Renner Berthing <emil.renner.berthing@...onical.com>,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Ben Dooks <ben.dooks@...ive.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110
VisionFive 2 board device tree
On Thu, Feb 23, 2023 at 04:50:20PM +0800, Hal Feng wrote:
> On Tue, 21 Feb 2023 16:03:08 +0100, Emil Renner Berthing wrote:
> > On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@...rfivetech.com> wrote:
> >> From: Emil Renner Berthing <kernel@...il.dk>
> >>
> >> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> >> which has version A and version B. Support booting and basic
> >> clock/reset/pinctrl/uart drivers.
> >>
> >> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> >> Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
> >> Co-developed-by: Jianlong Huang <jianlong.huang@...rfivetech.com>
> >> Signed-off-by: Jianlong Huang <jianlong.huang@...rfivetech.com>
> >> Co-developed-by: Hal Feng <hal.feng@...rfivetech.com>
> >> Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> >> ---
> >> arch/riscv/boot/dts/starfive/Makefile | 6 +-
> >> .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
> >> .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
> >> .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
> >> 4 files changed, 246 insertions(+), 1 deletion(-)
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >>
> >> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> >> index 039c143cba33..cd73519b907b 100644
> >> --- a/arch/riscv/boot/dts/starfive/Makefile
> >> +++ b/arch/riscv/boot/dts/starfive/Makefile
> >> @@ -1,2 +1,6 @@
> >> # SPDX-License-Identifier: GPL-2.0
> >> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
> >> +
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
If you could rebase on top of v6.3-rc1 for the next version & use ARCH_
not SOC_ here that'd be great.
> >> +/ {
> >> + aliases {
> >> + serial0 = &uart0;
> >> + i2c0 = &i2c0;
> >> + i2c2 = &i2c2;
> >> + i2c5 = &i2c5;
> >> + i2c6 = &i2c6;
> >
> > Let's keep these sorted alphabetically.
>
> OK, will fix it.
>
> > It would be great to have some sort of order to this file so it's
> > obvious where to add new nodes. I suggest we do
> > - root node
> > - external clocks
> > - other node references in alphabetical order
> >
> > You're almost there with this patch except the uart0 node is out of place.
>
> Will fix accordingly. Thanks for your suggestions.
With Emil's suggestions implemented:
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Thanks,
Conor.
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