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Message-ID: <20230302092928.60943-1-hejunhao3@huawei.com>
Date: Thu, 2 Mar 2023 17:29:28 +0800
From: Junhao He <hejunhao3@...wei.com>
To: <will@...nel.org>, <linux-kernel@...r.kernel.org>,
<jonathan.cameron@...wei.com>, <mark.rutland@....com>
CC: <linux-arm-kernel@...ts.infradead.org>,
<zhangshaokun@...ilicon.com>, <catalin.marinas@....com>,
<kernel-team@...roid.com>, <linuxarm@...wei.com>,
<yangyicong@...wei.com>, <f.fangjian@...wei.com>,
<shenyang39@...wei.com>, <prime.zeng@...ilicon.com>,
<hejunhao3@...wei.com>
Subject: [PATCH] perf cs-etm: add error logging to cs_etm_is_etmv4()
On the HiSilicon platform, there is one ETM per logic core.
When setting up SMT, not every process has an ETM. So the path
".../cs_etm/cpux/trcidr/trcidr0" does not exist, the function
perf_pmu__scan_file() return an error. However, the command
'perf record' will returns silently and don't print.
After this patch, log a error when read fails that makes it easy
for users to debug.
root@...alhost:/# perf record -e /cs_etm/@...ra_smb0/ -C 3 uname -a
cs_etm: can't read file cpu3/trcidr/trcidr0
root@...alhost:/#
Signed-off-by: Junhao He <hejunhao3@...wei.com>
---
tools/perf/arch/arm/util/cs-etm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c
index 7f71c8a237ff..19ea17430399 100644
--- a/tools/perf/arch/arm/util/cs-etm.c
+++ b/tools/perf/arch/arm/util/cs-etm.c
@@ -585,7 +585,6 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused,
static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu)
{
- bool ret = false;
char path[PATH_MAX];
int scan;
unsigned int val;
@@ -600,9 +599,10 @@ static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu)
/* The file was read successfully, we have a winner */
if (scan == 1)
- ret = true;
+ return true;
- return ret;
+ pr_err("%s: can't read file %s\n", CORESIGHT_ETM_PMU_NAME, path);
+ return false;
}
static int cs_etm_get_ro(struct perf_pmu *pmu, int cpu, const char *path)
--
2.33.0
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