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Message-ID: <f2660adc-e6c8-9de6-e1d6-7abdc7ad7249@linaro.org>
Date:   Mon, 6 Mar 2023 11:30:01 +0100
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Rohit Agarwal <quic_rohiagar@...cinc.com>, agross@...nel.org,
        andersson@...nel.org, lee@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, mani@...nel.org,
        lpieralisi@...nel.org, kw@...ux.com, bhelgaas@...gle.com,
        manivannan.sadhasivam@...aro.org
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org
Subject: Re: [PATCH 5/6] ARM: dts: qcom: sdx65-mtp: Enable PCIE0 PHY



On 6.03.2023 06:25, Rohit Agarwal wrote:
> Enable PCIE0 PHY on SDX65 MTP for PCIE EP.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
> ---
Status should go last. It would be nice if you could update
that for the other nodes in this dt while at it.

Konrad
>  arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> index 85ea02d..86bb853 100644
> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> @@ -245,6 +245,13 @@
>  	status = "okay";
>  };
>  
> +&pcie0_phy {
> +	status = "okay";
> +
> +	vdda-phy-supply = <&vreg_l1b_1p2>;
> +	vdda-pll-supply = <&vreg_l4b_0p88>;
> +};
> +
>  &qpic_bam {
>  	status = "okay";
>  };

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