linux-kernel - [PATCH v4] soc: qcom: llcc: Fix slice configuration values for SC8280XP

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20230306135527.509796-1-abel.vesa@linaro.org>
Date:   Mon,  6 Mar 2023 15:55:27 +0200
From:   Abel Vesa <abel.vesa@...aro.org>
To:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Sai Prakash Ranjan <quic_saipraka@...cinc.com>,
        Juerg Haefliger <juerg.haefliger@...onical.com>,
        Johan Hovold <johan@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        stable@...r.kernel.org, Johan Hovold <johan+linaro@...nel.org>
Subject: [PATCH v4] soc: qcom: llcc: Fix slice configuration values for SC8280XP

The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
LLCC config registers, which means it is writing beyond the upper limit
of the ATTR0_CFGn and ATTR1_CFGn range of registers. But the most obvious
impact is the fact that the mentioned slices do not get configured at all,
which will result in reduced performance. Fix that by using the slice ID
values taken from the latest LLCC SC table.

Fixes: ec69dfbdc426 ("soc: qcom: llcc: Add sc8180x and sc8280xp configurations")
Cc: stable@...r.kernel.org	# 5.19+
Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
Tested-by: Juerg Haefliger <juerg.haefliger@...onical.com>
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@...cinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Reviewed-by: Johan Hovold <johan+linaro@...nel.org>
---

The v3 is here:
https://lore.kernel.org/all/20230219165701.2557446-1-abel.vesa@linaro.org/

Changes since v3:
 * explicitly mentioned in the commit message the fact that some random
   registers might get written and the fact that there is an impact
   on performance.
 * Added Johan's R-b tag

Changes since v2:
 * specifically mentioned the 3 slice IDs that are being fixed and
   what is happening without this patch
 * added stabke Cc line
 * added Juerg's T-b tag
 * added Sai's R-b tag
 * added Konrad's A-b tag

Changes since v1:
 * dropped the LLCC_GPU and LLCC_WRCACHE max_cap changes
 * took the new values from documentatio this time rather than
   downstream kernel

 drivers/soc/qcom/llcc-qcom.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 23ce2f78c4ed..26efe12012a0 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -191,9 +191,9 @@ static const struct llcc_slice_config sc8280xp_data[] = {
 	{ LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
 	{ LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
 	{ LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
-	{ LLCC_CVPFW,    32, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
-	{ LLCC_CPUSS1,   33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
-	{ LLCC_CPUHWT,   36, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
+	{ LLCC_CVPFW,    17, 512,  1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+	{ LLCC_CPUSS1,   3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+	{ LLCC_CPUHWT,   5, 512,  1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
 };
 
 static const struct llcc_slice_config sdm845_data[] =  {
-- 
2.34.1