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Message-Id: <167816282864.1458033.14750605365789550573.b4-ty@kernel.org>
Date: Mon, 6 Mar 2023 20:20:26 -0800
From: Bjorn Andersson <andersson@...nel.org>
To: Konrad Dybcio <konrad.dybcio@...aro.org>,
Abel Vesa <abel.vesa@...aro.org>,
Sai Prakash Ranjan <quic_saipraka@...cinc.com>,
Johan Hovold <johan@...nel.org>,
Juerg Haefliger <juerg.haefliger@...onical.com>,
Andy Gross <agross@...nel.org>
Cc: stable@...r.kernel.org, linux-arm-msm@...r.kernel.org,
Johan Hovold <johan+linaro@...nel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4] soc: qcom: llcc: Fix slice configuration values for SC8280XP
On Mon, 6 Mar 2023 15:55:27 +0200, Abel Vesa wrote:
> The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> LLCC config registers, which means it is writing beyond the upper limit
> of the ATTR0_CFGn and ATTR1_CFGn range of registers. But the most obvious
> impact is the fact that the mentioned slices do not get configured at all,
> which will result in reduced performance. Fix that by using the slice ID
> values taken from the latest LLCC SC table.
>
> [...]
Applied, thanks!
[1/1] soc: qcom: llcc: Fix slice configuration values for SC8280XP
commit: 77bf4b3ed42e31d29b255fcd6530fb7a1e217e89
Best regards,
--
Bjorn Andersson <andersson@...nel.org>
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