linux-kernel - Re: [RFC PATCH V2 0/1] x86: cpu topology fix and question on x86_max

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Message-ID: <3bc616e8a513d4bfef2fb2d824f7ca8e8815bc77.camel@intel.com>
Date:   Tue, 7 Mar 2023 16:10:14 +0000
From:   "Zhang, Rui" <rui.zhang@...el.com>
To:     "tglx@...utronix.de" <tglx@...utronix.de>,
        "peterz@...radead.org" <peterz@...radead.org>
CC:     "Brown, Len" <len.brown@...el.com>,
        "zhang.jia@...ux.alibaba.com" <zhang.jia@...ux.alibaba.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "x86@...nel.org" <x86@...nel.org>
Subject: Re: [RFC PATCH V2 0/1] x86: cpu topology fix and question on
 x86_max_cores

Hi, all,

sorry for the late followup.

On Tue, 2023-02-21 at 16:26 +0800, Zhang Rui wrote:
> > > I thought of improving this by parsing all the valid APIC-IDs in
> > > MADT
> > > during BSP bootup, and get such information by decoding the APIC-
> > > IDs
> > > using the APIC-ID layout information retrieved from BSP. But this
> > > is
> > > likely to be a fertile new source of bugs as Dave concerned.
> > 
> > The APIC-IDs are only usefull if there is an architected scheme how
> > they
> > are assigned. Is there such a thing?
> 
> I don't know.
> Do you think it helps if the APIC-ID layout are defined to be
> identical
> across all CPUs?
> In this case, BSP knows the APIC-ID layout of itself and this can
> apply
> to the other APIC-IDs.

Yeah, I have confirmed with Len that the APIC-ID layouts are identical
across all CPUs on each single system.

> 
> > The SDM is not helpful at all, but according to the ACPI spec there
> > exists:
> > 
> >   Processor Properties Topology Table (PPTT)
> > 
> > That table actually provides pretty much what we are looking for,
> > but
> > that table is optional and there is actually code for that in the
> > kernel, which is ARM64 specific.
> > 
> > So while this would be useful it's not usable on x86 because that
> > would
> > make too much sense, right?
> 
> Thanks for pointing to this.
> 
> I got a brief view of PPTT. So far, my understanding is that PPTT
> provides
> 1. the cpu Hierarchy, but package level only. There may be multiple
> levels but it does not tell us if it is a Die, Module or Core.
> 2. the cache Hierarchy
> 
> I need to find one real PPTT implementation to see how it works.

I got one PPTT dump and also checked the kernel pptt parsing code.
Based on current PPTT definition, it is true that it can only tell
1. a thread (a Processor Hierarchy Node Structure with "Processor is a
Thread" flag set)
2. a CPU(core) (a Processor Hierarchy Node Structure with "Processor is
a Thread" flag cleared)
3. a package (a Processor Hierarchy Node Structure with "Physical
package" flag set)

We can get useful information like total packages, number of cores in a
package, number of smt siblings etc. But, say, if there is another
level between Core and package, it cannot tell if it is a
Die/Tile/Module. So far, this does not show a strong advantage compared
with the MADT solution, which doesn't depend on new firmware support.

thanks,
rui