linux-kernel - Re: [PATCH v4 6/9] arm64: dts: qcom: sa8775p-ride: enable the SPI node

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CACMJSetFuejNBPQBr8OBeq-edqhwNZfQ+Uz6iBJYf_kt+i_OeQ@mail.gmail.com>
Date:   Wed, 8 Mar 2023 13:36:03 +0100
From:   Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>
Cc:     Bartosz Golaszewski <brgl@...ev.pl>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 6/9] arm64: dts: qcom: sa8775p-ride: enable the SPI node

On Wed, 8 Mar 2023 at 11:58, Konrad Dybcio <konrad.dybcio@...aro.org> wrote:
>
>
>
> On 8.03.2023 11:40, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> >
> > Enable the SPI interface exposed on the sa8775p-ride development board.
> >
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> > index 5fdce8279537..d01ca3a9ee37 100644
> > --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> > @@ -14,6 +14,7 @@ / {
> >       aliases {
> >               serial0 = &uart10;
> >               i2c18 = &i2c18;
> > +             spi16 = &spi16;
> >       };
> >
> >       chosen {
> > @@ -40,12 +41,25 @@ &sleep_clk {
> >       clock-frequency = <32764>;
> >  };
> >
> > +&spi16 {
> > +     pinctrl-0 = <&qup_spi16_default>;
> > +     pinctrl-names = "default";
> > +     status = "okay";
> > +};
> > +
> >  &tlmm {
> >       qup_uart10_default: qup-uart10-state {
> >               pins = "gpio46", "gpio47";
> >               function = "qup1_se3";
> >       };
> >
> > +     qup_spi16_default: qup-spi16-state {
> > +             pins = "gpio86", "gpio87", "gpio88", "gpio89";
> Rather weird to have an identical configuration for all
> MOSI/MISO/CS/CLK pins.. Please doublecheck
>

This is in line with many other boards in arch/arm64/boot/dts/qcom/
that have the same config for all SPI pins. Some of them unnecessarily
split the config into separate state nodes with the same config
though.

Bart

> Konrad
> > +             function = "qup2_se2";
> > +             drive-strength = <6>;
> > +             bias-disable;
> > +     };
> > +
> >       qup_i2c18_default: qup-i2c18-state {
> >               pins = "gpio95", "gpio96";
> >               function = "qup2_se4";